| V1 |
smoke |
kmac_smoke |
19.030s |
984.518us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.760s |
54.417us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.790s |
51.758us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
8.090s |
1.451ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
7.410s |
4.712ms |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.450s |
188.020us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.790s |
51.758us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.410s |
4.712ms |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
1.610s |
17.260us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
2.170s |
29.751us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
28.675m |
75.549ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
10.697m |
15.219ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
30.700m |
169.821ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
29.080m |
387.089ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
24.521m |
128.032ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
15.090s |
5.179ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
28.024m |
42.555ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
29.669m |
99.491ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
3.780s |
96.065us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
3.150s |
84.939us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
1.995m |
2.482ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
13.560s |
10.758ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
41.090s |
8.723ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
52.310s |
2.852ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
3.550m |
43.673ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
8.960s |
3.410ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
3.740s |
111.036us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
14.060s |
550.204us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
2.000s |
31.250us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
58.250s |
62.789ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
2.370s |
43.886us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
7.515m |
11.404ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
1.730s |
45.904us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.690s |
66.509us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
3.310s |
334.042us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
3.310s |
334.042us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.760s |
54.417us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.790s |
51.758us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.410s |
4.712ms |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.270s |
116.359us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.760s |
54.417us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.790s |
51.758us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
7.410s |
4.712ms |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.270s |
116.359us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
2.300s |
48.399us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
2.300s |
48.399us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
2.300s |
48.399us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
2.300s |
48.399us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
3.040s |
108.422us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.006m |
13.685ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
3.750s |
160.123us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
3.750s |
160.123us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
2.370s |
43.886us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
19.030s |
984.518us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
1.995m |
2.482ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
2.300s |
48.399us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.006m |
13.685ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.006m |
13.685ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.006m |
13.685ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
19.030s |
984.518us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
2.370s |
43.886us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.006m |
13.685ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
4.486m |
18.163ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
19.030s |
984.518us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
2.050m |
2.427ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |