KMAC/UNMASKED Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	31.360s	3.539ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.710s	30.048us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.920s	29.092us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.770s	3.854ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.550s	1.506ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.100s	173.770us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.920s	29.092us	1	1	100.00
		kmac_csr_aliasing	7.550s	1.506ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.700s	11.515us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.210s	65.062us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	41.780m	462.827ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.230m	12.888ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.682m	61.248ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.830s	1.123ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.963m	107.095ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.785m	95.543ms	1	1	100.00
		kmac_test_vectors_shake_128	1.910m	14.934ms	1	1	100.00
		kmac_test_vectors_shake_256	3.436m	41.811ms	1	1	100.00
		kmac_test_vectors_kmac	2.270s	35.545us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.960s	218.216us	1	1	100.00
V2	sideload	kmac_sideload	3.133m	25.974ms	1	1	100.00
V2	app	kmac_app	4.815m	264.116ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	21.540s	784.639us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.482m	80.370ms	1	1	100.00
V2	error	kmac_error	3.156m	13.906ms	1	1	100.00
V2	key_error	kmac_key_error	3.360s	513.497us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.770s	276.163us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	7.060s	622.592us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	8.460s	571.107us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	9.200s	1.198ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.380s	43.673us	1	1	100.00
V2	stress_all	kmac_stress_all	3.480m	13.672ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.820s	51.641us	1	1	100.00
V2	alert_test	kmac_alert_test	1.920s	16.588us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.580s	138.222us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.580s	138.222us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.710s	30.048us	1	1	100.00
		kmac_csr_rw	1.920s	29.092us	1	1	100.00
		kmac_csr_aliasing	7.550s	1.506ms	1	1	100.00
		kmac_same_csr_outstanding	2.150s	42.458us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.710s	30.048us	1	1	100.00
		kmac_csr_rw	1.920s	29.092us	1	1	100.00
		kmac_csr_aliasing	7.550s	1.506ms	1	1	100.00
		kmac_same_csr_outstanding	2.150s	42.458us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.990s	103.085us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.990s	103.085us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.990s	103.085us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.990s	103.085us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.200s	495.848us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	21.590s	1.611ms	1	1	100.00
		kmac_tl_intg_err	2.490s	75.959us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.490s	75.959us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.380s	43.673us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	31.360s	3.539ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.133m	25.974ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.990s	103.085us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	21.590s	1.611ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	21.590s	1.611ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	21.590s	1.611ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	31.360s	3.539ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.380s	43.673us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	21.590s	1.611ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.968m	2.416ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	31.360s	3.539ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	49.340s	1.269ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.9619468996048781620332844239636104910962997983400046296597599491894321271771
      Line 223, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1269494945 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1269494945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---