MBX Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 57.000s 4.387ms 1 1 100.00
V1 csr_hw_reset mbx_csr_hw_reset 10.000s 14.052us 1 1 100.00
V1 csr_rw mbx_csr_rw 9.000s 13.150us 1 1 100.00
V1 csr_bit_bash mbx_csr_bit_bash 8.000s 225.928us 1 1 100.00
V1 csr_aliasing mbx_csr_aliasing 8.000s 120.613us 1 1 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 4.000s 1.117us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 9.000s 13.150us 1 1 100.00
mbx_csr_aliasing 8.000s 120.613us 1 1 100.00
V1 TOTAL 5 6 83.33
V2 mbx_stress mbx_stress 13.000s 9.318ms 0 1 0.00
mbx_stress_zero_delays 27.000s 3.672ms 1 1 100.00
V2 mbx_imbx_oob mbx_imbx_oob 39.000s 17.931ms 1 1 100.00
V2 alert_test mbx_alert_test 4.000s 54.386us 1 1 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 14.000s 2.064us 0 1 0.00
V2 tl_d_illegal_access mbx_tl_errors 14.000s 2.064us 0 1 0.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 10.000s 14.052us 1 1 100.00
mbx_csr_rw 9.000s 13.150us 1 1 100.00
mbx_csr_aliasing 8.000s 120.613us 1 1 100.00
mbx_same_csr_outstanding 6.000s 23.743us 1 1 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 10.000s 14.052us 1 1 100.00
mbx_csr_rw 9.000s 13.150us 1 1 100.00
mbx_csr_aliasing 8.000s 120.613us 1 1 100.00
mbx_same_csr_outstanding 6.000s 23.743us 1 1 100.00
V2 TOTAL 4 6 66.67
V2S tl_intg_err mbx_sec_cm 4.000s 38.665us 1 1 100.00
mbx_tl_intg_err 11.000s 22.223us 0 1 0.00
V2S TOTAL 1 2 50.00
TOTAL 10 14 71.43

Failure Buckets