ROM_CTRL/32KB Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.330s 488.978us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 4.520s 1.107ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.050s 177.513us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.050s 259.470us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.550s 1.696ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.100s 141.406us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.050s 177.513us 1 1 100.00
rom_ctrl_csr_aliasing 3.550s 1.696ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.580s 730.552us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.260s 731.166us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.990s 580.405us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 15.840s 2.254ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.200s 396.495us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.470s 266.737us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.370s 165.791us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.370s 165.791us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 4.520s 1.107ms 1 1 100.00
rom_ctrl_csr_rw 5.050s 177.513us 1 1 100.00
rom_ctrl_csr_aliasing 3.550s 1.696ms 1 1 100.00
rom_ctrl_same_csr_outstanding 3.860s 370.916us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 4.520s 1.107ms 1 1 100.00
rom_ctrl_csr_rw 5.050s 177.513us 1 1 100.00
rom_ctrl_csr_aliasing 3.550s 1.696ms 1 1 100.00
rom_ctrl_same_csr_outstanding 3.860s 370.916us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 14.400s 805.031us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.527m 416.387us 1 1 100.00
rom_ctrl_tl_intg_err 21.500s 647.341us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.527m 416.387us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.527m 416.387us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.527m 416.387us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.527m 416.387us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.330s 488.978us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.330s 488.978us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.330s 488.978us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.500s 647.341us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.200s 396.495us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 58.250s 7.685ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 14.400s 805.031us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.527m 416.387us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.003m 17.157ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00