ROM_CTRL/64KB Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.780s 312.394us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.090s 971.416us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.950s 417.598us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.480s 555.710us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.510s 319.680us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.620s 219.279us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.950s 417.598us 1 1 100.00
rom_ctrl_csr_aliasing 6.510s 319.680us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.160s 292.084us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.480s 1.414ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.220s 219.005us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.830s 7.098ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.480s 8.291ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.290s 295.612us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.000s 628.620us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.000s 628.620us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.090s 971.416us 1 1 100.00
rom_ctrl_csr_rw 6.950s 417.598us 1 1 100.00
rom_ctrl_csr_aliasing 6.510s 319.680us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.650s 1.308ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.090s 971.416us 1 1 100.00
rom_ctrl_csr_rw 6.950s 417.598us 1 1 100.00
rom_ctrl_csr_aliasing 6.510s 319.680us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.650s 1.308ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 21.720s 760.189us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.200m 1.342ms 1 1 100.00
rom_ctrl_tl_intg_err 1.099m 6.343ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.200m 1.342ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.200m 1.342ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.200m 1.342ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.200m 1.342ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.780s 312.394us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.780s 312.394us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.780s 312.394us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.099m 6.343ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.480s 8.291ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.344m 37.051ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 21.720s 760.189us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.200m 1.342ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 46.090s 3.464ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00