RV_TIMER Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.540s	16.311us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.880s	23.002us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.800s	50.928us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.240s	91.148us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.760s	50.057us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.680s	20.689us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.800s	50.928us	1	1	100.00
		rv_timer_csr_aliasing	1.760s	50.057us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	3.540s	3.323ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.200s	1.695ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.043m	92.669ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.043m	92.669ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.740s	3.820ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.870s	27.293us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.500s	14.417us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.450s	82.300us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.450s	82.300us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.880s	23.002us	1	1	100.00
		rv_timer_csr_rw	1.800s	50.928us	1	1	100.00
		rv_timer_csr_aliasing	1.760s	50.057us	1	1	100.00
		rv_timer_same_csr_outstanding	1.700s	20.689us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.880s	23.002us	1	1	100.00
		rv_timer_csr_rw	1.800s	50.928us	1	1	100.00
		rv_timer_csr_aliasing	1.760s	50.057us	1	1	100.00
		rv_timer_same_csr_outstanding	1.700s	20.689us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.230s	335.820us	1	1	100.00
		rv_timer_tl_intg_err	2.300s	206.694us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.300s	206.694us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	35.360s	8.008ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.380s	19.423us	1	1	100.00
		rv_timer_max	1.510s	12.470us	1	1	100.00
		TOTAL			19	19	100.00