SPI_DEVICE/1R1W Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.722m	425.484ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.010s	214.341us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.150s	184.881us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.870s	6.002ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.460s	788.718us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.820s	300.201us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.150s	184.881us	1	1	100.00
		spi_device_csr_aliasing	6.460s	788.718us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.630s	28.121us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.650s	50.477us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.740s	22.731us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.580s	2.811us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.530s	6.823us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.900s	87.190us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.900s	87.190us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.240s	2.216ms	1	1	100.00
		spi_device_tpm_sts_read	1.550s	76.948us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	14.360s	4.974ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.240s	415.357us	1	1	100.00
		spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	10.490s	5.224ms	1	1	100.00
		spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	10.490s	5.224ms	1	1	100.00
		spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	5.210s	867.330us	1	1	100.00
		spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	5.210s	867.330us	1	1	100.00
		spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	5.210s	867.330us	1	1	100.00
		spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	5.210s	867.330us	1	1	100.00
		spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	5.210s	867.330us	1	1	100.00
		spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.220s	1.106ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.880s	389.381us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.880s	389.381us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.880s	389.381us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.770s	144.061us	1	1	100.00
		spi_device_read_buffer_direct	4.140s	1.334ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.880s	389.381us	1	1	100.00
		spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.572m	92.371ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.710s	2.917ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.710s	2.917ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.722m	425.484ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.288m	131.645ms	1	1	100.00
V2	stress_all	spi_device_stress_all	8.350m	157.621ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.670s	14.072us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.700s	27.108us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.210s	199.560us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.210s	199.560us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.010s	214.341us	1	1	100.00
		spi_device_csr_rw	2.150s	184.881us	1	1	100.00
		spi_device_csr_aliasing	6.460s	788.718us	1	1	100.00
		spi_device_same_csr_outstanding	2.530s	526.239us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.010s	214.341us	1	1	100.00
		spi_device_csr_rw	2.150s	184.881us	1	1	100.00
		spi_device_csr_aliasing	6.460s	788.718us	1	1	100.00
		spi_device_same_csr_outstanding	2.530s	526.239us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.900s	363.642us	1	1	100.00
		spi_device_tl_intg_err	12.160s	1.165ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.160s	1.165ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	54.080s	8.967ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.48047606357397458060136199753445554990651524134894311142415167130112224934136
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1674187 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[57])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1674187 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1674187 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[953])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.98540388923450968143026042435288857125881199037987179239901331047980640916067
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4200830 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf59372 [111101011001001101110010] vs 0x0 [0])
        UVM_ERROR @   4220830 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa6e5d1 [101001101110010111010001] vs 0x0 [0])
        UVM_ERROR @   4314830 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf636d2 [111101100011011011010010] vs 0x0 [0])
        UVM_ERROR @   4389830 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x750087 [11101010000000010000111] vs 0x0 [0])
        UVM_ERROR @   4430830 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xea40d2 [111010100100000011010010] vs 0x0 [0])