SPI_HOST Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	9.000s	489.566us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	56.803us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	21.803us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	37.334us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	71.817us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	25.020us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	21.803us	1	1	100.00
		spi_host_csr_aliasing	4.000s	71.817us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	158.686us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	20.876us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	20.360us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	4.000s	41.143us	1	1	100.00
		spi_host_error_cmd	4.000s	34.636us	1	1	100.00
		spi_host_event	12.000s	890.959us	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	172.334us	1	1	100.00
V2	speed	spi_host_speed	5.000s	172.334us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	172.334us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	7.000s	253.059us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	104.671us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	172.334us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	172.334us	1	1	100.00
V2	duplex	spi_host_smoke	9.000s	489.566us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	9.000s	489.566us	1	1	100.00
V2	stress_all	spi_host_stress_all	8.000s	618.512us	1	1	100.00
V2	spien	spi_host_spien	8.000s	859.937us	1	1	100.00
V2	stall	spi_host_status_stall	17.000s	4.417ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	32.000s	3.126ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	4.000s	41.143us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	16.291us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	67.724us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	95.364us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	95.364us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	56.803us	1	1	100.00
		spi_host_csr_rw	4.000s	21.803us	1	1	100.00
		spi_host_csr_aliasing	4.000s	71.817us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	23.347us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	56.803us	1	1	100.00
		spi_host_csr_rw	4.000s	21.803us	1	1	100.00
		spi_host_csr_aliasing	4.000s	71.817us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	23.347us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	364.203us	1	1	100.00
		spi_host_sec_cm	4.000s	105.540us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	364.203us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	9.200m	16.343ms	1	1	100.00
		TOTAL			26	26	100.00