SRAM_CTRL/MAIN Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 42.670s 431.221us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.640s 44.077us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.800s 41.746us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.010s 31.168us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.690s 40.556us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.250s 367.767us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.800s 41.746us 1 1 100.00
sram_ctrl_csr_aliasing 1.690s 40.556us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 1.775m 9.734ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 1.670m 10.233ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 11.394m 99.229ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 4.296m 20.963ms 1 1 100.00
V2 bijection sram_ctrl_bijection 12.722m 98.372ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 7.934m 40.045ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 40.330s 60.098ms 1 1 100.00
V2 executable sram_ctrl_executable 10.015m 91.636ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 41.010s 834.942us 1 1 100.00
sram_ctrl_partial_access_b2b 5.093m 35.817ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 10.110s 4.623ms 1 1 100.00
sram_ctrl_throughput_w_partial_write 18.360s 758.191us 1 1 100.00
sram_ctrl_throughput_w_readback 22.210s 817.278us 1 1 100.00
V2 regwen sram_ctrl_regwen 3.518m 4.450ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 5.580s 1.300ms 1 1 100.00
V2 stress_all sram_ctrl_stress_all 17.675m 60.805ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.730s 12.053us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 2.910s 245.993us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 2.910s 245.993us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.640s 44.077us 1 1 100.00
sram_ctrl_csr_rw 1.800s 41.746us 1 1 100.00
sram_ctrl_csr_aliasing 1.690s 40.556us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.500s 23.913us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.640s 44.077us 1 1 100.00
sram_ctrl_csr_rw 1.800s 41.746us 1 1 100.00
sram_ctrl_csr_aliasing 1.690s 40.556us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.500s 23.913us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 17.530s 3.706ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.580s 4.486us 0 1 0.00
sram_ctrl_tl_intg_err 2.710s 481.049us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.580s 4.486us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.710s 481.049us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 3.518m 4.450ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 3.518m 4.450ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.800s 41.746us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 10.015m 91.636ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 10.015m 91.636ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 10.015m 91.636ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 40.330s 60.098ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 4.890s 1.331ms 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 17.530s 3.706ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 4.650s 3.868ms 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 42.670s 431.221us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 42.670s 431.221us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 10.015m 91.636ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.580s 4.486us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 40.330s 60.098ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.580s 4.486us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.580s 4.486us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 42.670s 431.221us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.580s 4.486us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 16.760s 1.598ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets