SRAM_CTRL/RET Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.053m	2.600ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.920s	15.480us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.700s	31.191us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.410s	161.419us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.860s	20.461us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.190s	54.681us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.700s	31.191us	1	1	100.00
		sram_ctrl_csr_aliasing	1.860s	20.461us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.440s	901.421us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.440s	266.414us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	4.538m	10.907ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.041m	5.458ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	55.630s	18.110ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.457m	74.750ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.840s	536.555us	1	1	100.00
V2	executable	sram_ctrl_executable	10.822m	30.042ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.340s	1.094ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.409m	14.959ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	18.410s	115.748us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.920s	54.867us	1	1	100.00
		sram_ctrl_throughput_w_readback	35.690s	871.820us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.811m	14.113ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.820s	51.171us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	26.628m	34.478ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.670s	10.855us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.330s	222.199us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.330s	222.199us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.920s	15.480us	1	1	100.00
		sram_ctrl_csr_rw	1.700s	31.191us	1	1	100.00
		sram_ctrl_csr_aliasing	1.860s	20.461us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	23.014us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.920s	15.480us	1	1	100.00
		sram_ctrl_csr_rw	1.700s	31.191us	1	1	100.00
		sram_ctrl_csr_aliasing	1.860s	20.461us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	23.014us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.630s	1.604ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.740s	1.777us	0	1	0.00
		sram_ctrl_tl_intg_err	3.400s	260.659us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.740s	1.777us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.400s	260.659us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.811m	14.113ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.811m	14.113ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.700s	31.191us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.822m	30.042ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.822m	30.042ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.822m	30.042ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.840s	536.555us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.020s	73.385us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.630s	1.604ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.100s	100.925us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.053m	2.600ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.053m	2.600ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.822m	30.042ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.740s	1.777us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.840s	536.555us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.740s	1.777us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.740s	1.777us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.053m	2.600ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.740s	1.777us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.809m	983.453us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.10844115530372900365257742577109413296498642139921790893607258038279881054265
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1776714 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1776714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---