UART Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: 12e45f3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.030s	499.733us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.520s	23.304us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.460s	16.829us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.020s	93.788us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.530s	20.067us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.540s	38.997us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.460s	16.829us	1	1	100.00
		uart_csr_aliasing	1.530s	20.067us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.181m	144.395ms	1	1	100.00
V2	parity	uart_smoke	2.030s	499.733us	1	1	100.00
		uart_tx_rx	1.181m	144.395ms	1	1	100.00
V2	parity_error	uart_intr	33.800s	29.873ms	1	1	100.00
		uart_rx_parity_err	2.245m	105.165ms	1	1	100.00
V2	watermark	uart_tx_rx	1.181m	144.395ms	1	1	100.00
		uart_intr	33.800s	29.873ms	1	1	100.00
V2	fifo_full	uart_fifo_full	43.760s	87.345ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	15.670s	10.543ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	4.154m	180.853ms	1	1	100.00
V2	rx_frame_err	uart_intr	33.800s	29.873ms	1	1	100.00
V2	rx_break_err	uart_intr	33.800s	29.873ms	1	1	100.00
V2	rx_timeout	uart_intr	33.800s	29.873ms	1	1	100.00
V2	perf	uart_perf	9.883m	20.185ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.280s	2.484ms	1	1	100.00
V2	line_loopback	uart_loopback	3.280s	2.484ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.185m	111.435ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	10.750s	34.469ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.250s	8.036ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	4.200s	2.456ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.958m	39.850ms	1	1	100.00
V2	stress_all	uart_stress_all	3.134m	124.966ms	1	1	100.00
V2	alert_test	uart_alert_test	1.400s	53.187us	1	1	100.00
V2	intr_test	uart_intr_test	1.570s	37.409us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.040s	146.558us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.040s	146.558us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.520s	23.304us	1	1	100.00
		uart_csr_rw	1.460s	16.829us	1	1	100.00
		uart_csr_aliasing	1.530s	20.067us	1	1	100.00
		uart_same_csr_outstanding	1.570s	65.329us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.520s	23.304us	1	1	100.00
		uart_csr_rw	1.460s	16.829us	1	1	100.00
		uart_csr_aliasing	1.530s	20.067us	1	1	100.00
		uart_same_csr_outstanding	1.570s	65.329us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.860s	857.567us	1	1	100.00
		uart_tl_intg_err	2.150s	104.146us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.150s	104.146us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	19.050s	2.604ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00