CHIP Simulation Results

Monday June 02 2025 17:06:05 UTC

GitHub Revision: `12e45f3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.993m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.993m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.174m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.699m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	2.237m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.184m	5.214ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.184m	5.214ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.184m	5.214ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.030s	10.200us	0	1	0.00
		chip_sw_example_manufacturer	3.931m		0	1	0.00
		chip_sw_example_concurrency	4.867m	4.956ms	1	1	100.00
		chip_sw_uart_smoketest_signed	13.815s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.110s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.560s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.560s		0	1	0.00
V1	xbar_smoke	xbar_smoke	10.080s	12.294us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.732m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.880m	8.389ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.598m	4.700ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.378m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.486m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.423m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.186m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.540s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.540s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.142m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.066m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	3.259m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	3.259m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.277m	3.783ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.496m	4.229ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.309m	14.072ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.498s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.544s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	8.896m	12.214ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.854m	5.490ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.667m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.667m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	18.410s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.065m	3.789ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.065m	3.789ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.182m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.783m	5.970ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.079m	4.213ms	1	1	100.00
		chip_sw_aes_idle	3.587m	3.428ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.727m	4.641ms	1	1	100.00
		chip_sw_kmac_idle	4.550m	5.304ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.271m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.114m	12.022ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.532m	12.023ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.274m	12.015ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	17.179s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.483s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.664s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.618s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.410s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.349s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.179s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.483s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.664s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.618s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.410s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.349s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.259s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.133m	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.360s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.880s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.420s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.841s		0	1	0.00
		chip_sw_clkmgr_jitter	4.314m	4.891ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.541m	4.817ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.932s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	49.040s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.910s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	58.740s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	47.580s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	51.510s	10.280us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.835s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.968s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.690s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.864s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.791m	15.149ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.854m	12.622ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.065m	3.789ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	15.075s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.854m	12.622ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.922s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	10.964s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	16.161s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	1.025m		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.812s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.791m	15.149ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.309m	14.072ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	25.638m	20.015ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.735m	7.035ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.570m	9.134ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.737m	5.251ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.791m	15.149ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.664s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.178s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.791m	15.149ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.577s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.570m	9.134ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.037s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.512s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.517s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.749s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.444s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.629s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.178s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	56.441s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.273s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	56.441s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	56.441s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	56.441s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.245m	7.089ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	28.173s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	18.900s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	22.544s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.474s		0	1	0.00
		chip_sw_lc_ctrl_transition	56.441s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.360m	9.774ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.518m	12.408ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.247s		0	1	0.00
		chip_prim_tl_access	11.529m	22.478ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.179s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.483s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.664s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.618s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.410s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.349s		0	1	0.00
		chip_rv_dm_lc_disabled	8.896m	12.214ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.260m	3.704ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.133m	10.220us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.079m	4.704ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.587m	3.428ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.582m	4.412ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	50.360s	10.360us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.727m	4.641ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.947m	3.825ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.142m	4.708ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	49.420s	10.360us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.360m	9.774ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	56.441s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	45.000s	10.320us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.662m	5.856ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.550m	5.304ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.688s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.688s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.973s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.759m	4.304ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.115s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.360m	9.774ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.880s	10.200us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	17.163s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.259s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.079m	4.213ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.079m	4.213ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.079m	4.213ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.386m	5.032ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.518m	12.408ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.518m	12.408ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.739m	8.802ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.841s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.247s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.791m	15.149ms	1	1	100.00
		chip_sw_data_integrity_escalation	3.259m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	56.441s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.386m	5.032ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.360m	9.774ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.739m	8.802ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.739m	3.722ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.386m	5.032ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.360m	9.774ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.739m	8.802ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.739m	3.722ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	56.441s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.999s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.273s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	28.173s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	18.900s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	22.544s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.474s		0	1	0.00
		chip_sw_lc_ctrl_transition	56.441s		0	1	0.00
		chip_prim_tl_access	11.529m	22.478ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	11.529m	22.478ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	15.692s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	23.296s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.968s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.259s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.133m	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.360s	10.360us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.880s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.420s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.841s		0	1	0.00
		chip_sw_clkmgr_jitter	4.314m	4.891ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.094m	9.938ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.094m	9.938ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.519m	5.869ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.425m	5.494ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.043m	5.344ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.420m	6.631ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.188m	4.851ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.142m	4.143ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.739m	3.722ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	25.638m	20.015ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	25.638m	20.015ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.339m	5.333ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.279m	4.642ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.768m	3.566ms	1	1	100.00
		chip_sw_csrng_smoketest	3.781m	5.660ms	1	1	100.00
		chip_sw_gpio_smoketest	4.684m	5.566ms	1	1	100.00
		chip_sw_hmac_smoketest	4.627m	4.268ms	1	1	100.00
		chip_sw_kmac_smoketest	3.920m	3.551ms	1	1	100.00
		chip_sw_otbn_smoketest	4.332m	4.122ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.717m	3.386ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.411m	3.798ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.014m	4.870ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.896m	4.093ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	4.019m	3.054ms	1	1	100.00
		chip_sw_uart_smoketest	3.957m	5.452ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	15.962s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	13.815s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.732m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.250s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.368m	5.706ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.390m	6.069ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.657m	5.396ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.389m	4.497ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.852s		0	1	0.00
		chip_rv_dm_lc_disabled	8.896m	12.214ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	22.215s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.990s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.155s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.003s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.852s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.087s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.508s		0	1	0.00
		rom_volatile_raw_unlock	11.401s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.561s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.165m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.273m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.380m	4.562ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.380m	4.562ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.560s		0	1	0.00
		chip_same_csr_outstanding	16.310s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.560s		0	1	0.00
		chip_same_csr_outstanding	16.310s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.539m	452.362us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	10.200s	12.280us	1	1	100.00
		xbar_smoke_large_delays	4.234m	2.317ms	1	1	100.00
		xbar_smoke_slow_rsp	5.293m	2.097ms	1	1	100.00
		xbar_random_zero_delays	28.180s	29.780us	1	1	100.00
		xbar_random_large_delays	5.222m	2.788ms	1	1	100.00
		xbar_random_slow_rsp	4.021m	1.554ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.087m	216.461us	1	1	100.00
		xbar_error_and_unmapped_addr	27.650s	23.274us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	10.940s	23.855us	1	1	100.00
		xbar_error_and_unmapped_addr	27.650s	23.274us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.358m	527.485us	1	1	100.00
		xbar_access_same_device_slow_rsp	33.850m	12.869ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	26.200s	73.388us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	13.376m	2.200ms	1	1	100.00
		xbar_stress_all_with_error	2.659m	175.064us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	51.130m	7.976ms	1	1	100.00
		xbar_stress_all_with_reset_error	20.594m	2.476ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.331s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.922s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.444s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.884s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.348s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.225s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.510s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.070s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.014s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.161s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.127s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.498s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.897s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.057s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.957s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.104s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.558s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.895s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.720s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.975s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.828s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.890s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.601s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.950s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.344s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.726s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.130s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.540s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.768s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.092s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.606s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.984s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.862s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.375s		0	1	0.00
		rom_e2e_asm_init_dev	11.222s		0	1	0.00
		rom_e2e_asm_init_prod	11.603s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.097s		0	1	0.00
		rom_e2e_asm_init_rma	11.585s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.772s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.289s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.669s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.527s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.485m	5.008ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.335m	3.970ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.886s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.470s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.477s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.973s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.791m	15.149ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.448s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.684m	15.301ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	14.496s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.903s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.886s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.470s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.477s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.984s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.142s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.608s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.500m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.247m	15.599ms	1	1	100.00
		chip_plic_all_irqs_0	10.424m	7.590ms	1	1	100.00
		chip_plic_all_irqs_10	9.961m	6.482ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.221m	5.069ms	1	1	100.00
		chip_sw_dma_abort	4.444m	4.062ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.904s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.176s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.893s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.559s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.266s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.438s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.208s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.128s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.385s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.327s		0	1	0.00
		chip_sw_mbx_smoketest	4.661m	5.027ms	1	1	100.00
		TOTAL			75	247	30.36

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.62033555896835826730488613234463636998281573495712043814645521792292982230987
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (581806)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 217.221s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.23524687869666688042481469114626743010406926304711404428555109739888456112800
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (5a408d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 184.211s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.35181037385294417154278792086019524666034505118518472173742481213111714431528
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (6d195f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 177.724s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.83890486186133109689883365210934490922567625639347292513552074472068162244091
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (9fbe42)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 173.802s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.49477288613593607030204976255194036625589989635974587104377890783559815807436
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (6bb02c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 169.656s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.114257703575747071656143328119167524696736686487001094796364086856771106111209
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.43189225223570669677724673067711578843068716622202705975178626535299624289427
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.64929442506937130138847656910173159720248110128318454159553975848116801114744
    Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.102527505936984831906132468991589793092426365362398047600927914961969582712386
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.108264590438290046667323783455202314077675860377236836357931573253284055532777
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.29380266104096144135392469860755343035079608486961310959173402159733875468143
Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12015.196451 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.196451 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.14995522886076948928887596002328419183375194009283654732814282948419948354525
Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12022.325141 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.325141 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.40660937998768252212094857378023149426980028421572300447567180074350311319887
Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12023.302405 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12023.302405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.30236923684353589960651910131245350888104978479538670182867058270436803611436
Line 444, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12014.935126 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.935126 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.93450043402236668768065941928286663071026639583936389239983994821660396176173
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.74230206348418100788991120400635898306873671333048782800650591844132164339793
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.45563228213694805076785653850652200631291547375051221900193659002047045102447
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.15904258458596687352282308075185607096409911326050825443036196698424882551821
Line 515, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20015.274848 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20015.274848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.90197953155742609775624740397850672565427366300528701873051758797867178337856
Line 475, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18016.179121 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.179121 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.43627718223178628943400052824817626073097929102776629966459531875000997136156
Line 471, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18019.438945 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18019.438945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.1259458868057763133352944789272043275922144709593928958734882454596265755444
Line 488, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9774.396776 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (39850867058103234943819901592396957932535229219819700583976599344766204309050 [0x581aca9c057c9c23890968ebe3381c5f1bcc0b7a3d9bfa34837e53d50f38ee3a] vs 109368956391085181572888139732537184295351126946689422964972166051699993320437 [0xf1cca2b96699342299c04e5ba9ebcb588e457deadf43e9459cce30fe60a39bf5])
  UVM_INFO @ 9774.396776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.51588297027184874503411372888204146230597275477507530730735574237213664180515
Line 490, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7089.491640 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (25630790310261961789209108671215801607178469522776080582856104035996171864984 [0x38aa8362a874ce0f9a37672f1204ae1b5b19dea6a85028202ad5b739d9cd8b98] vs 17951062005435317513926064682346756808968210938709736908913622755050158577037 [0x27aff0e804f2209c492f3ead6bd099e9950a145a0d9dd610a9272fd4adec558d])
  UVM_INFO @ 7089.491640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.37060374067009484496862252155692834749918476793349306333314704655104886307255
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3783.094950 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'hbc8faa08  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h0  a_user: 'h2694b  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3783.094950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.39254157992661874103511381850688568583891514847273705346762788335422933559739
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4228.619185 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'hc019413a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h34  a_opcode: 'h1  a_user: 'h248d0  d_param: 'h0  d_source: 'h34  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4228.619185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.87205376760370870913885640490121013909739589236478573673221531173792480034809
    Line 684, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.30576517779577423492941764483354588702043240958021148442179347910384432478956
    Line 503, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4700.446700 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4700.446700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.72330906304410836476721830951835192437930280925565847057602592504689404159344
    Line 742, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9133.505040 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9133.505040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.62424884516596793463826181620572794255907589671380621865059551028151108491681
    Line 455, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5868.957224 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5868.957224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.83720699494734979378871761788261376466558509576785981053001233673709622181370
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5493.644622 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5493.644622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.74534753537002379139769553178839617608721606280261359507809779424253488248712
    Line 463, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3788.797030 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3788.797030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.43388368345819323006055291652669123655352759959042910241141801553832724200753
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6630.809584 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6630.809584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.46504148636124316601875947150159662747089161203236438425822973930701492268485
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.33505786333048575064661742220060011784810782725148962263146132239829349366900
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4562.127852 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4562.127852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.48468274187992770840804421429616565099563925841173432444098732949979348034220
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14072.436264 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14072.436264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:689) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert unexpectedly fired in cycle *. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.110084548341816873336205458886256361223859523401771628996506148278539385730801
    Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 3970.001550 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:689) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (1 [0x1] vs 0 [0x0]) Major alert unexpectedly fired in cycle 0.
  UVM_INFO @ 3970.001550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.48519245772021240552145990554368299026572526578246400375834695010716403794545
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.14279731067246188130160576938380415507539961208901822501449288441700916049706
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4062.150518 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4062.150518 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```