AES/MASKED Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	65.918us	1	1	100.00
V1	smoke	aes_smoke	5.000s	199.112us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	133.705us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	105.776us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	784.248us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	322.244us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	391.100us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	105.776us	1	1	100.00
		aes_csr_aliasing	5.000s	322.244us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	199.112us	1	1	100.00
		aes_config_error	5.000s	283.047us	1	1	100.00
		aes_stress	8.000s	736.401us	1	1	100.00
V2	key_length	aes_smoke	5.000s	199.112us	1	1	100.00
		aes_config_error	5.000s	283.047us	1	1	100.00
		aes_stress	8.000s	736.401us	1	1	100.00
V2	back2back	aes_stress	8.000s	736.401us	1	1	100.00
		aes_b2b	14.000s	656.752us	1	1	100.00
V2	backpressure	aes_stress	8.000s	736.401us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	199.112us	1	1	100.00
		aes_config_error	5.000s	283.047us	1	1	100.00
		aes_stress	8.000s	736.401us	1	1	100.00
		aes_alert_reset	6.000s	201.984us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	55.118us	1	1	100.00
		aes_config_error	5.000s	283.047us	1	1	100.00
		aes_alert_reset	6.000s	201.984us	1	1	100.00
V2	trigger_clear_test	aes_clear	7.000s	102.817us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	355.091us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	201.984us	1	1	100.00
V2	stress	aes_stress	8.000s	736.401us	1	1	100.00
V2	sideload	aes_stress	8.000s	736.401us	1	1	100.00
		aes_sideload	6.000s	66.959us	1	1	100.00
V2	deinitialization	aes_deinit	6.000s	190.140us	1	1	100.00
V2	stress_all	aes_stress_all	53.000s	2.428ms	1	1	100.00
V2	alert_test	aes_alert_test	5.000s	65.989us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	164.078us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	164.078us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	133.705us	1	1	100.00
		aes_csr_rw	4.000s	105.776us	1	1	100.00
		aes_csr_aliasing	5.000s	322.244us	1	1	100.00
		aes_same_csr_outstanding	5.000s	99.416us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	133.705us	1	1	100.00
		aes_csr_rw	4.000s	105.776us	1	1	100.00
		aes_csr_aliasing	5.000s	322.244us	1	1	100.00
		aes_same_csr_outstanding	5.000s	99.416us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	63.993us	1	1	100.00
V2S	fault_inject	aes_fi	6.000s	945.322us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	5.000s	87.313us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	63.214us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	63.214us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	63.214us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	63.214us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	296.962us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	2.146ms	1	1	100.00
		aes_tl_intg_err	5.000s	206.386us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	206.386us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	201.984us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	63.214us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	199.112us	1	1	100.00
		aes_stress	8.000s	736.401us	1	1	100.00
		aes_alert_reset	6.000s	201.984us	1	1	100.00
		aes_core_fi	5.000s	177.630us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	63.214us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	80.440us	1	1	100.00
		aes_stress	8.000s	736.401us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	736.401us	1	1	100.00
		aes_sideload	6.000s	66.959us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	80.440us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	80.440us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	80.440us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	80.440us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	80.440us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	736.401us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	736.401us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	945.322us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	945.322us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	5.000s	87.313us	1	1	100.00
		aes_ctr_fi	5.000s	77.627us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	945.322us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	945.322us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	5.000s	87.313us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	87.313us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	945.322us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	945.322us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	5.000s	77.627us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	945.322us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	5.000s	87.313us	1	1	100.00
		aes_ctr_fi	5.000s	77.627us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	201.984us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	945.322us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	5.000s	87.313us	1	1	100.00
		aes_ctr_fi	5.000s	77.627us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	945.322us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	5.000s	87.313us	1	1	100.00
		aes_ctr_fi	5.000s	77.627us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	945.322us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	5.000s	77.627us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	945.322us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	5.000s	87.313us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.000s	42.885us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.3116747287158404095534671504347895074069660561367363798220255049353306787247
      Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.64551837052452858411896511531265142359235957151818064541715651466438387266382
      Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  42884821 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @  42884821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---