DMA Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	1.244ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	9.000s	1.387ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	1.305ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	72.683us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	12.995us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	11.000s	305.352us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	937.285us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	40.259us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	12.995us	1	1	100.00
		dma_csr_aliasing	8.000s	937.285us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.583m	22.145ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	4.233m	27.556ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	8.283m	82.683ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	4.367m	80.034ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	4.233m	27.556ms	1	1	100.00
V2	dma_abort	dma_abort	8.000s	471.533us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.567m	6.445ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	29.900us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	629.293us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	629.293us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	72.683us	1	1	100.00
		dma_csr_rw	4.000s	12.995us	1	1	100.00
		dma_csr_aliasing	8.000s	937.285us	1	1	100.00
		dma_same_csr_outstanding	6.000s	99.667us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	72.683us	1	1	100.00
		dma_csr_rw	4.000s	12.995us	1	1	100.00
		dma_csr_aliasing	8.000s	937.285us	1	1	100.00
		dma_same_csr_outstanding	6.000s	99.667us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	1.017ms	1	1	100.00
		dma_generic_stress	4.367m	80.034ms	1	1	100.00
		dma_handshake_stress	4.233m	27.556ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	1.360ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.983m	13.083ms	1	1	100.00
		dma_longer_transfer	6.000s	149.937us	1	1	100.00
		TOTAL			21	21	100.00