EDN Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.770s	49.862us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.960s	18.786us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.840s	23.751us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.680s	517.864us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.930s	59.225us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.830s	20.372us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.840s	23.751us	1	1	100.00
		edn_csr_aliasing	1.930s	59.225us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.930s	45.411us	1	1	100.00
V2	csrng_commands	edn_genbits	1.930s	45.411us	1	1	100.00
V2	genbits	edn_genbits	1.930s	45.411us	1	1	100.00
V2	interrupts	edn_intr	1.820s	23.021us	1	1	100.00
V2	alerts	edn_alert	1.800s	56.400us	1	1	100.00
V2	errs	edn_err	1.710s	34.357us	1	1	100.00
V2	disable	edn_disable	1.770s	11.863us	1	1	100.00
		edn_disable_auto_req_mode	1.930s	109.197us	1	1	100.00
V2	stress_all	edn_stress_all	4.960s	610.260us	1	1	100.00
V2	intr_test	edn_intr_test	1.760s	26.422us	1	1	100.00
V2	alert_test	edn_alert_test	1.760s	150.738us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.830s	72.347us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.830s	72.347us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.960s	18.786us	1	1	100.00
		edn_csr_rw	1.840s	23.751us	1	1	100.00
		edn_csr_aliasing	1.930s	59.225us	1	1	100.00
		edn_same_csr_outstanding	1.980s	21.391us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.960s	18.786us	1	1	100.00
		edn_csr_rw	1.840s	23.751us	1	1	100.00
		edn_csr_aliasing	1.930s	59.225us	1	1	100.00
		edn_same_csr_outstanding	1.980s	21.391us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.620s	1.025ms	1	1	100.00
		edn_tl_intg_err	2.730s	180.023us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.850s	27.637us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.800s	56.400us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.620s	1.025ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.620s	1.025ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.620s	1.025ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.620s	1.025ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.800s	56.400us	1	1	100.00
		edn_sec_cm	4.620s	1.025ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.800s	56.400us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.730s	180.023us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	48.960s	3.215ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00