HMAC Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.230s 208.523us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.660s 133.922us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.630s 18.415us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.830s 3.729ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.350s 164.506us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.580s 169.160us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.630s 18.415us 1 1 100.00
hmac_csr_aliasing 6.350s 164.506us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 22.280s 9.130ms 1 1 100.00
V2 back_pressure hmac_back_pressure 41.980s 2.197ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.600s 321.677us 1 1 100.00
hmac_test_sha384_vectors 20.650s 301.094us 1 1 100.00
hmac_test_sha512_vectors 19.520s 1.019ms 1 1 100.00
hmac_test_hmac256_vectors 9.590s 1.175ms 1 1 100.00
hmac_test_hmac384_vectors 10.020s 318.874us 1 1 100.00
hmac_test_hmac512_vectors 10.050s 294.230us 1 1 100.00
V2 burst_wr hmac_burst_wr 18.240s 4.137ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 7.961m 6.281ms 1 1 100.00
V2 error hmac_error 24.640s 9.687ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.588m 51.303ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.230s 208.523us 1 1 100.00
hmac_long_msg 22.280s 9.130ms 1 1 100.00
hmac_back_pressure 41.980s 2.197ms 1 1 100.00
hmac_datapath_stress 7.961m 6.281ms 1 1 100.00
hmac_burst_wr 18.240s 4.137ms 1 1 100.00
hmac_stress_all 16.159m 70.898ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.230s 208.523us 1 1 100.00
hmac_long_msg 22.280s 9.130ms 1 1 100.00
hmac_back_pressure 41.980s 2.197ms 1 1 100.00
hmac_datapath_stress 7.961m 6.281ms 1 1 100.00
hmac_wipe_secret 1.588m 51.303ms 1 1 100.00
hmac_test_sha256_vectors 8.600s 321.677us 1 1 100.00
hmac_test_sha384_vectors 20.650s 301.094us 1 1 100.00
hmac_test_sha512_vectors 19.520s 1.019ms 1 1 100.00
hmac_test_hmac256_vectors 9.590s 1.175ms 1 1 100.00
hmac_test_hmac384_vectors 10.020s 318.874us 1 1 100.00
hmac_test_hmac512_vectors 10.050s 294.230us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.230s 208.523us 1 1 100.00
hmac_long_msg 22.280s 9.130ms 1 1 100.00
hmac_back_pressure 41.980s 2.197ms 1 1 100.00
hmac_datapath_stress 7.961m 6.281ms 1 1 100.00
hmac_burst_wr 18.240s 4.137ms 1 1 100.00
hmac_error 24.640s 9.687ms 1 1 100.00
hmac_wipe_secret 1.588m 51.303ms 1 1 100.00
hmac_test_sha256_vectors 8.600s 321.677us 1 1 100.00
hmac_test_sha384_vectors 20.650s 301.094us 1 1 100.00
hmac_test_sha512_vectors 19.520s 1.019ms 1 1 100.00
hmac_test_hmac256_vectors 9.590s 1.175ms 1 1 100.00
hmac_test_hmac384_vectors 10.020s 318.874us 1 1 100.00
hmac_test_hmac512_vectors 10.050s 294.230us 1 1 100.00
hmac_stress_all 16.159m 70.898ms 1 1 100.00
V2 stress_all hmac_stress_all 16.159m 70.898ms 1 1 100.00
V2 alert_test hmac_alert_test 1.500s 32.577us 1 1 100.00
V2 intr_test hmac_intr_test 1.610s 16.323us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.310s 85.547us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.310s 85.547us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.660s 133.922us 1 1 100.00
hmac_csr_rw 1.630s 18.415us 1 1 100.00
hmac_csr_aliasing 6.350s 164.506us 1 1 100.00
hmac_same_csr_outstanding 2.790s 537.676us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.660s 133.922us 1 1 100.00
hmac_csr_rw 1.630s 18.415us 1 1 100.00
hmac_csr_aliasing 6.350s 164.506us 1 1 100.00
hmac_same_csr_outstanding 2.790s 537.676us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.780s 684.527us 1 1 100.00
hmac_tl_intg_err 2.300s 1.031ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.300s 1.031ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.230s 208.523us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.610s 632.209us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.798m 5.873ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.820s 157.446us 1 1 100.00
TOTAL 28 28 100.00