I2C Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: `fa1d963`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	13.840s	1.269ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	19.940s	887.555us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.840s	26.060us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.730s	60.760us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.320s	1.457ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.860s	66.391us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.720s	73.307us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.730s	60.760us	1	1	100.00
		i2c_csr_aliasing	1.860s	66.391us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.240s	97.036us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.755m	24.245ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	3.450m	48.540ms	1	1	100.00
V2	host_override	i2c_host_override	1.640s	79.692us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.322m	4.367ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	54.990s	5.458ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.800s	348.914us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.530s	332.764us	1	1	100.00
		i2c_host_fifo_reset_rx	3.050s	297.303us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.196m	8.643ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.560s	5.198ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.290s	196.902us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.110s	2.207ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.377m	14.304ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.530s	4.234ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	5.790s	435.324us	1	1	100.00
		i2c_target_intr_smoke	3.270s	2.894ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.140s	572.255us	1	1	100.00
		i2c_target_fifo_reset_tx	1.990s	178.601us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.750m	48.023ms	1	1	100.00
		i2c_target_stress_rd	5.790s	435.324us	1	1	100.00
		i2c_target_intr_stress_wr	5.420s	15.103ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.860s	5.169ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	20.880s	2.965ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.370s	4.610ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	9.870s	10.030ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.630s	1.856ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.710s	897.724us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	3.450m	48.540ms	1	1	100.00
		i2c_host_perf_precise	3.980s	1.662ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.560s	5.198ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.340s	153.864us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.820s	1.021ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.360s	529.220us	1	1	100.00
		i2c_target_nack_txstretch	1.810s	141.991us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.860s	463.770us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.770s	1.845ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.560s	39.223us	1	1	100.00
V2	intr_test	i2c_intr_test	1.580s	18.498us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.380s	176.901us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.380s	176.901us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.840s	26.060us	1	1	100.00
		i2c_csr_rw	1.730s	60.760us	1	1	100.00
		i2c_csr_aliasing	1.860s	66.391us	1	1	100.00
		i2c_same_csr_outstanding	1.750s	33.230us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.840s	26.060us	1	1	100.00
		i2c_csr_rw	1.730s	60.760us	1	1	100.00
		i2c_csr_aliasing	1.860s	66.391us	1	1	100.00
		i2c_same_csr_outstanding	1.750s	33.230us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.720s	140.582us	1	1	100.00
		i2c_sec_cm	1.700s	128.910us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.720s	140.582us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.380s	1.703ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.930s	61.575us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.430s	1.450ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.45793580793510756128495157704079408914489769227394563186621495960295377940875
Line 205, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 24245251095 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1579888

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.73456861965053793798850915367848493677916740399793159974054325897438798128652
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  61575269 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 175 [0xaf])
  UVM_INFO @  61575269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.113822315645888113724791294741203422428092584917291913692880956950592390543606
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10030459631 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10030459631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.55905460001253275391368976212061778924517854786303542541891531501125719958356
    Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1703196208 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1703196208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.113896019963387591204949534769576365173002200905602826970800131092665378684464
    Line 109, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1450027872 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
  UVM_INFO @ 1450027872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```