KEYMGR Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: `fa1d963`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.490s	2.009ms	1	1	100.00
V1	random	keymgr_random	5.730s	540.258us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.890s	59.145us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.700s	48.733us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.930s	1.750ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.590s	519.214us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.120s	188.592us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.700s	48.733us	0	1	0.00
		keymgr_csr_aliasing	6.590s	519.214us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	5.510s	117.002us	1	1	100.00
V2	sideload	keymgr_sideload	3.280s	175.546us	1	1	100.00
		keymgr_sideload_kmac	4.870s	376.178us	1	1	100.00
		keymgr_sideload_aes	3.780s	998.750us	1	1	100.00
		keymgr_sideload_otbn	5.100s	231.380us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.220s	137.634us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.970s	180.679us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.210s	118.406us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.740s	205.288us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	5.490s	268.096us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.320s	817.594us	1	1	100.00
V2	stress_all	keymgr_stress_all	15.580s	2.551ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.700s	11.218us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.720s	21.533us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.450s	61.449us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.450s	61.449us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.890s	59.145us	1	1	100.00
		keymgr_csr_rw	1.700s	48.733us	0	1	0.00
		keymgr_csr_aliasing	6.590s	519.214us	1	1	100.00
		keymgr_same_csr_outstanding	2.090s	20.012us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.890s	59.145us	1	1	100.00
		keymgr_csr_rw	1.700s	48.733us	0	1	0.00
		keymgr_csr_aliasing	6.590s	519.214us	1	1	100.00
		keymgr_same_csr_outstanding	2.090s	20.012us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
		keymgr_tl_intg_err	3.020s	347.747us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.170s	121.309us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.170s	121.309us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.170s	121.309us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.170s	121.309us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.900s	474.209us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.020s	347.747us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.170s	121.309us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	5.510s	117.002us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.730s	540.258us	1	1	100.00
		keymgr_csr_rw	1.700s	48.733us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.730s	540.258us	1	1	100.00
		keymgr_csr_rw	1.700s	48.733us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.730s	540.258us	1	1	100.00
		keymgr_csr_rw	1.700s	48.733us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.970s	180.679us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	5.490s	268.096us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	5.490s	268.096us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.730s	540.258us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	9.190s	1.214ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.580s	56.237us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.970s	180.679us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.580s	56.237us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.580s	56.237us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.580s	56.237us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.190s	548.848us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.580s	56.237us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	5.440s	1.034ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.88585968057726490653107936002084897132549359925650717207359893057659690986639
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @ 474208720 ps: (keymgr_csr_assert_fpv.sv:439) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @ 474208720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_csr_rw has 1 failures.

0.keymgr_csr_rw.106649264407446504197072643977065049383648576270283811684428261383012088021238
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  48733238 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  48733238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 0.keymgr_stress_all_with_rand_reset.28528127432979122079666824035562613655832056988328123809850702778236910334802
    Line 295, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1034453259 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1034453259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```