KEYMGR_DPE Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	13.270s	2.531ms	1	1	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	2.000s	26.537us	1	1	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.800s	15.206us	1	1	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	4.880s	3.095ms	1	1	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	2.980s	82.979us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.200s	74.683us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.800s	15.206us	1	1	100.00
		keymgr_dpe_csr_aliasing	2.980s	82.979us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	intr_test	keymgr_dpe_intr_test	1.680s	40.782us	1	1	100.00
V2	alert_test	keymgr_dpe_alert_test	1.580s	25.936us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.570s	275.796us	1	1	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.570s	275.796us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	2.000s	26.537us	1	1	100.00
		keymgr_dpe_csr_rw	1.800s	15.206us	1	1	100.00
		keymgr_dpe_csr_aliasing	2.980s	82.979us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.640s	250.941us	1	1	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	2.000s	26.537us	1	1	100.00
		keymgr_dpe_csr_rw	1.800s	15.206us	1	1	100.00
		keymgr_dpe_csr_aliasing	2.980s	82.979us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.640s	250.941us	1	1	100.00
V2		TOTAL			4	4	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	5.720s	1.329ms	1	1	100.00
		keymgr_dpe_tl_intg_err	5.040s	3.014ms	1	1	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.860s	795.591us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.860s	795.591us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.860s	795.591us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.860s	795.591us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	2.690s	48.896us	1	1	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	5.720s	1.329ms	1	1	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	5.720s	1.329ms	1	1	100.00
V2S		TOTAL			4	4	100.00
		TOTAL			14	14	100.00