KMAC/MASKED Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.129m	17.947ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.890s	29.947us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.820s	31.393us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.870s	1.003ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.040s	384.422us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	45.053us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.820s	31.393us	1	1	100.00
		kmac_csr_aliasing	6.040s	384.422us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.490s	16.369us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.990s	62.070us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	9.111m	129.129ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.631m	38.916ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.470s	6.190ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.630m	69.023ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.020s	1.676ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.938m	128.878ms	1	1	100.00
		kmac_test_vectors_shake_128	3.146m	53.568ms	1	1	100.00
		kmac_test_vectors_shake_256	2.387m	22.386ms	1	1	100.00
		kmac_test_vectors_kmac	3.260s	79.768us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.270s	94.060us	1	1	100.00
V2	sideload	kmac_sideload	42.600s	1.423ms	1	1	100.00
V2	app	kmac_app	4.383m	106.165ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.617m	38.050ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.058m	14.758ms	1	1	100.00
V2	error	kmac_error	2.766m	2.925ms	1	1	100.00
V2	key_error	kmac_key_error	3.910s	509.335us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.330s	490.104us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.990s	32.350us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	4.370s	1.092ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	7.220s	3.317ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.710s	53.460us	1	1	100.00
V2	stress_all	kmac_stress_all	22.255m	378.562ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.580s	21.447us	1	1	100.00
V2	alert_test	kmac_alert_test	1.690s	25.236us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.840s	148.246us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.840s	148.246us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.890s	29.947us	1	1	100.00
		kmac_csr_rw	1.820s	31.393us	1	1	100.00
		kmac_csr_aliasing	6.040s	384.422us	1	1	100.00
		kmac_same_csr_outstanding	2.590s	72.051us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.890s	29.947us	1	1	100.00
		kmac_csr_rw	1.820s	31.393us	1	1	100.00
		kmac_csr_aliasing	6.040s	384.422us	1	1	100.00
		kmac_same_csr_outstanding	2.590s	72.051us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.340s	275.742us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.340s	275.742us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.340s	275.742us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.340s	275.742us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.910s	735.925us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.285m	13.401ms	1	1	100.00
		kmac_tl_intg_err	3.780s	452.641us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.780s	452.641us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.710s	53.460us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.129m	17.947ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	42.600s	1.423ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.340s	275.742us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.285m	13.401ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.285m	13.401ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.285m	13.401ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.129m	17.947ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.710s	53.460us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.285m	13.401ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.739m	39.243ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.129m	17.947ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.350s	19.137us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.91299978368823478004435583383327695880817736807623464498033485234385045841819
      Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  19137168 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @  19137168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---