KMAC/UNMASKED Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	18.120s	2.103ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.770s	22.763us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.900s	274.508us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.260s	5.359ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.900s	305.057us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.680s	287.928us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.900s	274.508us	1	1	100.00
		kmac_csr_aliasing	3.900s	305.057us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.660s	22.522us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.940s	36.028us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	14.888m	27.986ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.293m	94.750ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.580s	3.619ms	1	1	100.00
		kmac_test_vectors_sha3_256	17.267m	18.101ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.506m	70.058ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.118m	179.798ms	1	1	100.00
		kmac_test_vectors_shake_128	1.950m	3.761ms	1	1	100.00
		kmac_test_vectors_shake_256	3.893m	67.170ms	1	1	100.00
		kmac_test_vectors_kmac	2.530s	60.305us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.750s	82.330us	1	1	100.00
V2	sideload	kmac_sideload	5.199m	39.371ms	1	1	100.00
V2	app	kmac_app	2.634m	19.283ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.359m	12.537ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.479m	9.894ms	1	1	100.00
V2	error	kmac_error	3.960m	114.274ms	1	1	100.00
V2	key_error	kmac_key_error	7.240s	1.518ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.810s	169.155us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	16.760s	4.389ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	13.710s	2.313ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	15.900s	4.617ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.840s	53.746us	1	1	100.00
V2	stress_all	kmac_stress_all	1.140m	7.575ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.620s	17.249us	1	1	100.00
V2	alert_test	kmac_alert_test	1.690s	47.814us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.180s	198.127us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.180s	198.127us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.770s	22.763us	1	1	100.00
		kmac_csr_rw	1.900s	274.508us	1	1	100.00
		kmac_csr_aliasing	3.900s	305.057us	1	1	100.00
		kmac_same_csr_outstanding	2.710s	36.449us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.770s	22.763us	1	1	100.00
		kmac_csr_rw	1.900s	274.508us	1	1	100.00
		kmac_csr_aliasing	3.900s	305.057us	1	1	100.00
		kmac_same_csr_outstanding	2.710s	36.449us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.760s	35.280us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.760s	35.280us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.760s	35.280us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.760s	35.280us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.050s	135.366us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	18.260s	3.189ms	1	1	100.00
		kmac_tl_intg_err	4.100s	775.102us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.100s	775.102us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.840s	53.746us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	18.120s	2.103ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.199m	39.371ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.760s	35.280us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	18.260s	3.189ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	18.260s	3.189ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	18.260s	3.189ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	18.120s	2.103ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.840s	53.746us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	18.260s	3.189ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	47.230s	13.572ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	18.120s	2.103ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.040s	42.578us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.20890064317252582278196905485050922735861707801266642407563701841140200861570
      Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  42577560 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
        UVM_INFO @  42577560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.105777648710349423014741809548191570986088939905379757786981040656990554635281
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @ 135366013 ps: (kmac_csr_assert_fpv.sv:525) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @ 135366013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---