fa1d963| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 1.550m | 24.100ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 29.011us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 21.234us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 5.000s | 57.684us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 11.512us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.340us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 21.234us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 11.512us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 28.000s | 3.397ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 56.000s | 4.463ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 7.000s | 1.624ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 38.927us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 3.000s | 1.977us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 3.000s | 1.977us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 29.011us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 21.234us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 11.512us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 38.194us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 29.011us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 21.234us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 11.512us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 38.194us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 18.832us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 8.523us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.82048942743916244751858448194968235505605323646705197275093350195514205110949
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1977226 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xa944944d a_data = 0x6069aa4c a_mask = 0x0 a_size = 0x0 a_param = 0x0 a_source = 0x9d a_opcode = PutFullData a_user = 0x27a2d d_data = 0x9a045cbe d_size = 0x2 d_param = 0x0 d_source = 0xad d_opcode = AccessAckData d_error = 0 d_user = 1011100100110 d_sink = 1 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1977226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.112135298308851436925964938724144611362297113502204965021406809369359090750841
Line 102, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 8522774 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xf5658fe8 a_data = 0x80ab54d9 a_mask = 0x1 a_size = 0x2 a_param = 0x0 a_source = 0x51 a_opcode = Get a_user = 0x27ca7 d_data = 0x2b8701a7 d_size = 0x1 d_param = 0x0 d_source = 0x70 d_opcode = AccessAckData d_error = 0 d_user = 10011010110001 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 8522774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.25171161328211986617609530514535705026999476629821737206512976702961538836545
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1339832 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x18f52488 a_data = 0xc7023ba8 a_mask = 0x0 a_size = 0x0 a_param = 0x0 a_source = 0x1 a_opcode = PutFullData a_user = 0x24584 d_data = 0x456b4115 d_size = 0x2 d_param = 0x0 d_source = 0xbf d_opcode = AccessAck d_error = 0 d_user = 1110111010101 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1339832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---