ROM_CTRL/32KB Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.220s 185.122us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.110s 129.451us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.300s 662.808us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.080s 553.401us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.840s 266.603us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.810s 634.705us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.300s 662.808us 1 1 100.00
rom_ctrl_csr_aliasing 3.840s 266.603us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.090s 163.557us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.260s 209.299us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.110s 636.110us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 14.620s 416.246us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 10.420s 2.028ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.490s 537.696us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.800s 863.348us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.800s 863.348us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.110s 129.451us 1 1 100.00
rom_ctrl_csr_rw 4.300s 662.808us 1 1 100.00
rom_ctrl_csr_aliasing 3.840s 266.603us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.530s 373.816us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.110s 129.451us 1 1 100.00
rom_ctrl_csr_rw 4.300s 662.808us 1 1 100.00
rom_ctrl_csr_aliasing 3.840s 266.603us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.530s 373.816us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 12.540s 406.558us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.874m 1.027ms 1 1 100.00
rom_ctrl_tl_intg_err 21.480s 757.462us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.874m 1.027ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.874m 1.027ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.874m 1.027ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.874m 1.027ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.220s 185.122us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.220s 185.122us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.220s 185.122us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.480s 757.462us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
rom_ctrl_kmac_err_chk 10.420s 2.028ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.552m 6.671ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 12.540s 406.558us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.874m 1.027ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 10.415m 27.258ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00