ROM_CTRL/64KB Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.410s 223.002us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.520s 804.314us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 9.030s 2.102ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.240s 376.614us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 8.670s 289.464us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.550s 222.409us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 9.030s 2.102ms 1 1 100.00
rom_ctrl_csr_aliasing 8.670s 289.464us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.810s 545.395us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.670s 555.370us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.660s 1.111ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 38.510s 7.988ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.120s 2.108ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.990s 1.070ms 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.920s 1.068ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.920s 1.068ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.520s 804.314us 1 1 100.00
rom_ctrl_csr_rw 9.030s 2.102ms 1 1 100.00
rom_ctrl_csr_aliasing 8.670s 289.464us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.090s 739.986us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.520s 804.314us 1 1 100.00
rom_ctrl_csr_rw 9.030s 2.102ms 1 1 100.00
rom_ctrl_csr_aliasing 8.670s 289.464us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.090s 739.986us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 37.270s 2.326ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.574m 2.051ms 1 1 100.00
rom_ctrl_tl_intg_err 1.091m 486.709us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.574m 2.051ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.574m 2.051ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.574m 2.051ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.574m 2.051ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.410s 223.002us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.410s 223.002us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.410s 223.002us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.091m 486.709us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.120s 2.108ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.407m 19.520ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 37.270s 2.326ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.574m 2.051ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.440m 9.809ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00