RV_TIMER Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.420s	20.344us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.540s	44.100us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.500s	14.534us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.170s	440.446us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.620s	85.637us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.490s	28.145us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.500s	14.534us	1	1	100.00
		rv_timer_csr_aliasing	1.620s	85.637us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.580s	1.067ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.260s	869.645us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.008m	132.556ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.008m	132.556ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.330s	6.308ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.470s	30.037us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.560s	12.037us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.830s	155.263us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.830s	155.263us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.540s	44.100us	1	1	100.00
		rv_timer_csr_rw	1.500s	14.534us	1	1	100.00
		rv_timer_csr_aliasing	1.620s	85.637us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	66.642us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.540s	44.100us	1	1	100.00
		rv_timer_csr_rw	1.500s	14.534us	1	1	100.00
		rv_timer_csr_aliasing	1.620s	85.637us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	66.642us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.560s	148.281us	1	1	100.00
		rv_timer_tl_intg_err	1.800s	158.631us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.800s	158.631us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	42.630s	5.822ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.410s	22.083us	1	1	100.00
		rv_timer_max	1.420s	115.688us	1	1	100.00
		TOTAL			19	19	100.00