SPI_DEVICE/1R1W Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.764m	167.541ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.150s	243.810us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.000s	63.938us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.440s	725.123us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.510s	2.541ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.590s	53.019us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.000s	63.938us	1	1	100.00
		spi_device_csr_aliasing	11.510s	2.541ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.500s	35.867us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.780s	61.531us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.810s	29.352us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.610s	8.142us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.630s	3.191us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.790s	64.990us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.790s	64.990us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.960s	982.423us	1	1	100.00
		spi_device_tpm_sts_read	1.680s	31.196us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.050s	119.780us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.830s	605.963us	1	1	100.00
		spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.550s	3.944ms	1	1	100.00
		spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.550s	3.944ms	1	1	100.00
		spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	14.830s	2.352ms	1	1	100.00
		spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	14.830s	2.352ms	1	1	100.00
		spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	14.830s	2.352ms	1	1	100.00
		spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	14.830s	2.352ms	1	1	100.00
		spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	14.830s	2.352ms	1	1	100.00
		spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.660s	129.815us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	36.880s	6.239ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	36.880s	6.239ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	36.880s	6.239ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.720s	410.076us	1	1	100.00
		spi_device_read_buffer_direct	3.390s	146.496us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	36.880s	6.239ms	1	1	100.00
		spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	12.500s	3.454ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	10.380s	6.941ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	10.380s	6.941ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.764m	167.541ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.371m	62.046ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.196m	32.987ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.600s	22.849us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.490s	14.745us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.680s	271.654us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.680s	271.654us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.150s	243.810us	1	1	100.00
		spi_device_csr_rw	3.000s	63.938us	1	1	100.00
		spi_device_csr_aliasing	11.510s	2.541ms	1	1	100.00
		spi_device_same_csr_outstanding	2.260s	48.998us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.150s	243.810us	1	1	100.00
		spi_device_csr_rw	3.000s	63.938us	1	1	100.00
		spi_device_csr_aliasing	11.510s	2.541ms	1	1	100.00
		spi_device_same_csr_outstanding	2.260s	48.998us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.930s	99.055us	1	1	100.00
		spi_device_tl_intg_err	10.450s	488.456us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.450s	488.456us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.359m	66.772ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.18363441180255710339630820260677129029435143452192152327610423573460914322519
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   6941895 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[87])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   6941895 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   6941895 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[983])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.38978917214781739038884696682620669546075380074946205793832595468624399300349
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    920567 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe16ca [11100001011011001010] vs 0x0 [0])
        UVM_ERROR @   1008567 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc2546 [11000010010101000110] vs 0x0 [0])
        UVM_ERROR @   1014567 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa08f14 [101000001000111100010100] vs 0x0 [0])
        UVM_ERROR @   1113567 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7d1fd1 [11111010001111111010001] vs 0x0 [0])
        UVM_ERROR @   1123567 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x598bee [10110011000101111101110] vs 0x0 [0])