SRAM_CTRL/MAIN Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.045m	943.986us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.930s	62.579us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.580s	50.156us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.550s	126.599us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.730s	27.743us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.140s	357.615us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.580s	50.156us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	27.743us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.919m	3.946ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	45.270s	1.916ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.696m	58.950ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.881m	57.364ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	8.502m	41.630ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.575m	21.717ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	8.160s	1.666ms	1	1	100.00
V2	executable	sram_ctrl_executable	29.970s	9.005ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.140s	465.920us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.008m	39.170ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	53.600s	801.944us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	46.970s	795.493us	1	1	100.00
		sram_ctrl_throughput_w_readback	15.160s	1.086ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.727m	296.327ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.420s	344.996us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	39.257m	114.542ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.540s	14.768us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.160s	43.721us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.160s	43.721us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.930s	62.579us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	50.156us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	27.743us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	45.161us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.930s	62.579us	1	1	100.00
		sram_ctrl_csr_rw	1.580s	50.156us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	27.743us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	45.161us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	19.830s	19.422ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.900s	3.428us	0	1	0.00
		sram_ctrl_tl_intg_err	2.580s	285.392us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.900s	3.428us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.580s	285.392us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.727m	296.327ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.727m	296.327ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.580s	50.156us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.970s	9.005ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.970s	9.005ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.970s	9.005ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	8.160s	1.666ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	8.210s	687.033us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	19.830s	19.422ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.280s	13.182ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.045m	943.986us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.045m	943.986us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.970s	9.005ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.900s	3.428us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	8.160s	1.666ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.900s	3.428us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.900s	3.428us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.045m	943.986us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.900s	3.428us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.910s	1.220ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.12284410310148108433683907329098721004072313357197539266192233220765753230444
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3428161 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3428161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---