SRAM_CTRL/RET Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.940s	4.285ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.910s	20.110us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.550s	33.675us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.110s	104.161us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.700s	23.965us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.880s	95.636us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.550s	33.675us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	23.965us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.990s	360.706us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.680s	382.097us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.282m	6.715ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.691m	1.670ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	11.230s	476.594us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.788m	9.610ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.130s	2.220ms	1	1	100.00
V2	executable	sram_ctrl_executable	11.328m	21.503ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.860s	969.008us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.748m	33.143ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.660s	51.208us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.028m	306.575us	1	1	100.00
		sram_ctrl_throughput_w_readback	8.070s	112.858us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.936m	2.648ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.510s	129.260us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	21.287m	25.710ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.800s	33.139us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.880s	89.819us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.880s	89.819us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.910s	20.110us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	33.675us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	23.965us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.600s	86.355us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.910s	20.110us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	33.675us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	23.965us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.600s	86.355us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.920s	3.442ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.530s	2.953us	0	1	0.00
		sram_ctrl_tl_intg_err	2.810s	212.926us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.530s	2.953us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.810s	212.926us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.936m	2.648ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.936m	2.648ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.550s	33.675us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	11.328m	21.503ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	11.328m	21.503ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	11.328m	21.503ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.130s	2.220ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.300s	62.013us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.920s	3.442ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.720s	99.855us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.940s	4.285ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.940s	4.285ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	11.328m	21.503ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.530s	2.953us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.130s	2.220ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.530s	2.953us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.530s	2.953us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.940s	4.285ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.530s	2.953us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.139m	2.757ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.59932900602394866120667334326389209836875000186059779898452363012674682555321
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  99855173 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x20) != exp (0x6e)
        UVM_INFO @  99855173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.16721773745246118564403736208856639359025735439751161297349029526906504088392
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2952857 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2952857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---