UART Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: fa1d963

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.030s	272.663us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.470s	51.968us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.380s	44.172us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.730s	646.481us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.640s	18.197us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.790s	83.480us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.380s	44.172us	1	1	100.00
		uart_csr_aliasing	1.640s	18.197us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.092m	77.209ms	1	1	100.00
V2	parity	uart_smoke	2.030s	272.663us	1	1	100.00
		uart_tx_rx	1.092m	77.209ms	1	1	100.00
V2	parity_error	uart_intr	1.758m	112.617ms	1	1	100.00
		uart_rx_parity_err	23.850s	90.762ms	1	1	100.00
V2	watermark	uart_tx_rx	1.092m	77.209ms	1	1	100.00
		uart_intr	1.758m	112.617ms	1	1	100.00
V2	fifo_full	uart_fifo_full	45.380s	173.662ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.429m	88.293ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	42.210s	181.265ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.758m	112.617ms	1	1	100.00
V2	rx_break_err	uart_intr	1.758m	112.617ms	1	1	100.00
V2	rx_timeout	uart_intr	1.758m	112.617ms	1	1	100.00
V2	perf	uart_perf	2.951m	5.644ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.940s	4.114ms	1	1	100.00
V2	line_loopback	uart_loopback	4.940s	4.114ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	40.620s	40.402ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	33.990s	29.954ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.880s	1.176ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	9.560s	5.606ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.224m	93.142ms	1	1	100.00
V2	stress_all	uart_stress_all	6.952m	260.539ms	1	1	100.00
V2	alert_test	uart_alert_test	1.380s	61.254us	1	1	100.00
V2	intr_test	uart_intr_test	1.460s	90.555us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.080s	32.099us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.080s	32.099us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.470s	51.968us	1	1	100.00
		uart_csr_rw	1.380s	44.172us	1	1	100.00
		uart_csr_aliasing	1.640s	18.197us	1	1	100.00
		uart_same_csr_outstanding	1.580s	42.934us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.470s	51.968us	1	1	100.00
		uart_csr_rw	1.380s	44.172us	1	1	100.00
		uart_csr_aliasing	1.640s	18.197us	1	1	100.00
		uart_same_csr_outstanding	1.580s	42.934us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.590s	72.105us	1	1	100.00
		uart_tl_intg_err	1.790s	197.948us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.790s	197.948us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	31.190s	9.144ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00