CHIP Simulation Results

Tuesday June 03 2025 17:04:18 UTC

GitHub Revision: `fa1d963`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.803m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.803m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.767m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.941m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.559m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.533m	4.851ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.533m	4.851ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.533m	4.851ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.640s	10.180us	0	1	0.00
		chip_sw_example_manufacturer	2.943m		0	1	0.00
		chip_sw_example_concurrency	3.620m	3.726ms	1	1	100.00
		chip_sw_uart_smoketest_signed	13.679s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	13.930s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.690s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.690s		0	1	0.00
V1	xbar_smoke	xbar_smoke	22.670s	61.337us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.382m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.459m	11.118ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.648m	4.201ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	30.458s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	20.836s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.804m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	24.261s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.920s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.920s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.748m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.445m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.963m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.963m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.995m	3.614ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.545m	5.353ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.423m	14.597ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.432s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.588s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	17.919m	28.564ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.242m	4.064ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	19.524m	18.025ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	19.524m	18.025ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.256s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.794m	6.244ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.794m	6.244ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.635m	18.017ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.870m	5.476ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.901m	3.772ms	1	1	100.00
		chip_sw_aes_idle	4.502m	5.655ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.213m	5.421ms	1	1	100.00
		chip_sw_kmac_idle	4.700m	5.102ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.975m	12.026ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.710m	12.017ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.218m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.434m	12.015ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.763s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.350s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.850s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.108s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.068s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.577s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.198s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.763s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.350s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.850s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.108s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.068s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.577s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.198s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.592s		0	1	0.00
		chip_sw_aes_enc_jitter_en	52.130s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.790s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.830s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	48.460s	10.400us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.144s		0	1	0.00
		chip_sw_clkmgr_jitter	3.222m	3.308ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.469m	5.330ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	14.849s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	46.930s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	49.060s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	46.160s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	46.310s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	53.790s	10.380us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.992s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.120s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.107s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.212s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.931m	14.034ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.838m	11.949ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.794m	6.244ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.023s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.838m	11.949ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.549s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	16.742s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	24.491s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	22.302s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.984s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.931m	14.034ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.423m	14.597ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	19.751m	20.015ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.228m	10.008ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.627m	9.531ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.207m	4.674ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.931m	14.034ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.845s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.685s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.931m	14.034ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.475s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.627m	9.531ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.408s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.504s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.630s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.311s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.817s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.069s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.685s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	14.439s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.503s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	14.439s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	14.439s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	14.439s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.028m	5.725ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.248s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.769s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.701s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.111s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.439s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.796m	9.888ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.145m	14.246ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.421s		0	1	0.00
		chip_prim_tl_access	13.413m	18.530ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.763s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.350s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.850s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.108s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.068s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.577s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.198s		0	1	0.00
		chip_rv_dm_lc_disabled	17.919m	28.564ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.450m	5.392ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	52.130s	10.100us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.260m	3.593ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.502m	5.655ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.806m	3.659ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	48.790s	10.180us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.213m	5.421ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.762m	5.174ms	1	1	100.00
		chip_sw_kmac_mode_kmac	6.111m	6.006ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	48.460s	10.400us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.796m	9.888ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	14.439s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	41.600s	10.300us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.535m	5.251ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.700m	5.102ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.472s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.472s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.456s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.554m	3.718ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.695s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.796m	9.888ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.830s	10.100us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	10.729s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.592s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.901m	3.772ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.901m	3.772ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.901m	3.772ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.569m	5.695ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.145m	14.246ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.145m	14.246ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.296m	5.909ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.144s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.421s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.931m	14.034ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.963m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	14.439s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.569m	5.695ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.796m	9.888ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.296m	5.909ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.603m	3.300ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.569m	5.695ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.796m	9.888ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.296m	5.909ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.603m	3.300ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	14.439s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.427s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.503s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.248s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.769s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.701s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.111s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.439s		0	1	0.00
		chip_prim_tl_access	13.413m	18.530ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	13.413m	18.530ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.154s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	14.309s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.120s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.592s		0	1	0.00
		chip_sw_aes_enc_jitter_en	52.130s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.790s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.830s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	48.460s	10.400us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.144s		0	1	0.00
		chip_sw_clkmgr_jitter	3.222m	3.308ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.110m	8.882ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.110m	8.882ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	6.104m	5.487ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.427m	4.674ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.942m	4.927ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.676m	5.971ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.967m	4.405ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.890m	5.002ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.603m	3.300ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	19.751m	20.015ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	19.751m	20.015ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.458m	4.269ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.065m	4.607ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.543m	5.273ms	1	1	100.00
		chip_sw_csrng_smoketest	3.973m	5.395ms	1	1	100.00
		chip_sw_gpio_smoketest	3.572m	5.942ms	1	1	100.00
		chip_sw_hmac_smoketest	3.859m	4.474ms	1	1	100.00
		chip_sw_kmac_smoketest	3.796m	3.494ms	1	1	100.00
		chip_sw_otbn_smoketest	4.538m	4.545ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.453m	4.599ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.219m	4.163ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.481m	4.599ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.840m	4.672ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.122m	3.561ms	1	1	100.00
		chip_sw_uart_smoketest	3.359m	4.809ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	35.379s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	13.679s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.382m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.247s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.731m	5.806ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.427m	3.844ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.672m	5.258ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.674m	4.555ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.431s		0	1	0.00
		chip_rv_dm_lc_disabled	17.919m	28.564ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.075s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.895s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.596s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.070s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.431s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.754s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.977s		0	1	0.00
		rom_volatile_raw_unlock	10.983s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.005s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.065m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.454m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.123m	3.724ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.123m	3.724ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.690s		0	1	0.00
		chip_same_csr_outstanding	9.550s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.690s		0	1	0.00
		chip_same_csr_outstanding	9.550s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.715m	264.517us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.060s	12.293us	1	1	100.00
		xbar_smoke_large_delays	5.078m	2.710ms	1	1	100.00
		xbar_smoke_slow_rsp	5.148m	2.004ms	1	1	100.00
		xbar_random_zero_delays	17.270s	14.482us	1	1	100.00
		xbar_random_large_delays	2.215m	1.191ms	1	1	100.00
		xbar_random_slow_rsp	12.126m	4.327ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.002m	102.924us	1	1	100.00
		xbar_error_and_unmapped_addr	1.453m	189.772us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.716m	317.088us	1	1	100.00
		xbar_error_and_unmapped_addr	1.453m	189.772us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.104m	143.697us	1	1	100.00
		xbar_access_same_device_slow_rsp	38.065m	15.065ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	40.010s	107.067us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	9.631m	1.545ms	1	1	100.00
		xbar_stress_all_with_error	12.503m	2.237ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.190m	115.739us	1	1	100.00
		xbar_stress_all_with_reset_error	21.806m	2.519ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.597s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.183s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.623s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.437s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.575s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.247s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.196s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.220s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.504s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.229s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.496s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.267s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.580s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	10.795s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	10.747s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.034s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.543s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.852s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.564s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.667s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.301s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.280s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.976s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.909s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.451s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.698s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.433s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.214s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.752s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.060s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.476s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.587s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.774s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.557s		0	1	0.00
		rom_e2e_asm_init_dev	12.357s		0	1	0.00
		rom_e2e_asm_init_prod	13.072s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.834s		0	1	0.00
		rom_e2e_asm_init_rma	11.530s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.421s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.491s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.822s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.034s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.491m	4.108ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.582m	4.854ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	13.153s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.345s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.138s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.963s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.931m	14.034ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.932s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.171m	12.463ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.405s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.934s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	13.153s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.345s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.138s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.434s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.088s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.808s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.365m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.546m	12.272ms	1	1	100.00
		chip_plic_all_irqs_0	9.571m	6.759ms	1	1	100.00
		chip_plic_all_irqs_10	10.034m	6.194ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.975m	4.742ms	1	1	100.00
		chip_sw_dma_abort	4.297m	3.676ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.611s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.612s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.282s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.027s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.823s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.309s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.213s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.665s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.116s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.156s		0	1	0.00
		chip_sw_mbx_smoketest	4.120m	3.843ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.4020221775840227388641612135854964826659812592422664390361975272165623536224
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1b518f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 161.342s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.26372119893472797328050477272675655543988048938163696212998886395459493011666
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (1ff569)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 167.705s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.87425991365452624472998026706381944076707332556602212283044623201208772007932
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (f346f2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 154.820s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.76091966524525851798264539188358668656176238653396518348111919800069043341963
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (4657c2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 136.844s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.29332228552001893798320739596424591803550503601021692975955196088664119813252
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (71ca00)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 157.286s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.8711627198449296974520739834490685994477812952442118737849062770036444835660
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.39928480633599161800442362885927081020596818702213823231874876355827898162756
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.104512111866224898809900375190220627777030486131363603871874749679569402133914
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.93873672891910370875509422585476424029583681454950374840128369630899608927600
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.35879376713278691399140297259346317690381013373508850429815844838436513575259
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.842027005532249914520717771113454931580336718103762387790105815948174038046
Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.379314 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.379314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.3725019148764373850700037311350234875752203586615644650622641094805925113868
Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12017.492922 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.492922 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.70847314022419971825191927711643518732834718113789834787736722218681805632951
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12017.565307 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.565307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.104628084924709758556667685113812478883369390340274523315149287966944682414961
Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12014.628530 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.628530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.4594567334684745683133065230463893437972505440280322761785357013204298200698
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.89410060843948454896437551789643764897065313868090925181459012299747936103177
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.65781846323279453743860196740324577122547341345197808099012104937426567684119
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.35677293254665545173691151282994972041211823802634086418494244429568495342877
Line 505, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20015.266513 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20015.266513 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.50806920043063778249290799282546852697317328111280239787384766647551192389734
Line 463, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18025.235810 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18025.235810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.44705313568031202089157117484348664113158183732354210056871322572684671784345
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18016.561192 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.561192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.52739217528830613933465000500095313280738308857126874390120087064251959205578
Line 471, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9888.104304 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (25415894324648325404175147528146147354799872336736293138033425834750175092671 [0x3830e2eb8ac52953b6132f0db968b63c60008022a4ab24d7f4dbeccdd4581fbf] vs 75127742745739003504695810910281850495258692762095204696601597705148217690061 [0xa618cba6cc2dd1cf86433369721dd8c2e889c10ae04d0690f189354480b407cd])
  UVM_INFO @ 9888.104304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.60158892119968316449093871307274697184405785543373614905361522664864076012989
Line 471, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5725.371896 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (108636948353072222331915492018951024092395052455753775539104077887157707611934 [0xf02e55723b34a7a975cbe051162764b0a630f010ba861fc3e5ca02255a3a1f1e] vs 17687123860614598315519660729766548799343171730791822966571779773439465942552 [0x271a8eae1e1c4a65709c414286757a5a335c752f8b7e5229af82eff88a72ee18])
  UVM_INFO @ 5725.371896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.22119362364097282775971392456584279104363608606272655430094888310777114675710
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3613.568805 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h547b89eb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h0  a_user: 'h26919  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3613.568805 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.94573805056103273262726631880493935039190919880360388218073678071182331827776
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5352.748137 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'ha6a04e73  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h0  a_user: 'h26921  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5352.748137 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.63951384564287077099672092913046118169170928547055699363154137939834211353244
    Line 586, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.12324110195317021355019278552126183817359016184528650006970695882643398388790
    Line 452, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4201.301022 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4201.301022 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.3258684417344715192487296377893885278490382606175707574864442247827209269997
    Line 724, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9530.730308 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9530.730308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.44799094786746862945099866659390600520662726713755787343629322947545726190564
    Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5487.377228 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5487.377228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.21843369981875217393625624561345172575606408595587500578090558189344648645515
    Line 472, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4674.485084 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4674.485084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.58851516634039860853197317630780958664625334346756083275413065696880997718243
    Line 455, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 6243.597022 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 6243.597022 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.100515236475485348549653842989385362677992474551266499212219244524251119166358
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5971.246240 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5971.246240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.4078858216091284325451163411047297084273204974611738311559795773540276767393
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35984) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.65724416228174747697063241343422178784254513924043849717406235503611182642271
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3723.701608 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35984) { a_addr: 'h1465413  a_data: 'h909f3a65  a_mask: 'h0  a_size: 'h0  a_param: 'h0  a_source: 'h5  a_opcode: 'h4  a_user: 'h27f40  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h0  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h4aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3723.701608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.73771152774181023566830540916860894484036420768879325669205697932230525751632
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14596.805788 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14596.805788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.13641527924668914425413803133686003828112020864989404754609734162609990629928
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.34163214326532141081781816638253490017327381951937246887074971981753015022477
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3675.699360 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3675.699360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```