CSRNG Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: `2e10a15`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	41.349us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	34.393us	1	1	100.00
V1	csr_rw	csrng_csr_rw	5.000s	71.615us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	15.000s	471.521us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	98.982us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	34.296us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	71.615us	1	1	100.00
		csrng_csr_aliasing	6.000s	98.982us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	7.000s	182.886us	1	1	100.00
V2	alerts	csrng_alert	11.000s	299.917us	1	1	100.00
V2	err	csrng_err	4.000s	2.882us	0	1	0.00
V2	cmds	csrng_cmds	24.000s	507.936us	1	1	100.00
V2	life cycle	csrng_cmds	24.000s	507.936us	1	1	100.00
V2	stress_all	csrng_stress_all	3.417m	5.072ms	1	1	100.00
V2	intr_test	csrng_intr_test	5.000s	34.345us	1	1	100.00
V2	alert_test	csrng_alert_test	4.000s	59.888us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	5.000s	41.075us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	5.000s	41.075us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	34.393us	1	1	100.00
		csrng_csr_rw	5.000s	71.615us	1	1	100.00
		csrng_csr_aliasing	6.000s	98.982us	1	1	100.00
		csrng_same_csr_outstanding	6.000s	156.241us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	34.393us	1	1	100.00
		csrng_csr_rw	5.000s	71.615us	1	1	100.00
		csrng_csr_aliasing	6.000s	98.982us	1	1	100.00
		csrng_same_csr_outstanding	6.000s	156.241us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	5.000s	45.520us	1	1	100.00
		csrng_tl_intg_err	9.000s	421.482us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	13.914us	1	1	100.00
		csrng_csr_rw	5.000s	71.615us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	11.000s	299.917us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	3.417m	5.072ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
		csrng_sec_cm	5.000s	45.520us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
		csrng_sec_cm	5.000s	45.520us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
		csrng_sec_cm	5.000s	45.520us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
		csrng_sec_cm	5.000s	45.520us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
		csrng_sec_cm	5.000s	45.520us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
		csrng_sec_cm	5.000s	45.520us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
		csrng_sec_cm	5.000s	45.520us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	11.000s	299.917us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	3.417m	5.072ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	11.000s	299.917us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	421.482us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
		csrng_sec_cm	5.000s	45.520us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
		csrng_sec_cm	5.000s	45.520us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	182.886us	1	1	100.00
		csrng_err	4.000s	2.882us	0	1	0.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	18.000s	328.468us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			17	19	89.47

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_control_fsm.sv,452): Assertion u_state_regs_A has failed has 1 failures:

Test csrng_err has 1 failures.

0.csrng_err.56806628803811286872969287910040102112857667908120519941035199734439964737344
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 2881896 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   2881896 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   2881896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 0.csrng_stress_all_with_rand_reset.14668385697773869193330064073995917712552008059860611751729228552811415840250
    Line 100, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 328468143 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 328468143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```