DMA Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	6.000s	506.480us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	400.339us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	380.055us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	58.075us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	24.306us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	13.000s	1.993ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	278.722us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	47.589us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	24.306us	1	1	100.00
		dma_csr_aliasing	6.000s	278.722us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	37.000s	7.297ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	2.100m	111.943ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	26.217m	513.625ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	5.100m	27.747ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	2.100m	111.943ms	1	1	100.00
V2	dma_abort	dma_abort	11.000s	1.292ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	3.017m	56.924ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	15.547us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	121.489us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	121.489us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	58.075us	1	1	100.00
		dma_csr_rw	4.000s	24.306us	1	1	100.00
		dma_csr_aliasing	6.000s	278.722us	1	1	100.00
		dma_same_csr_outstanding	6.000s	250.030us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	58.075us	1	1	100.00
		dma_csr_rw	4.000s	24.306us	1	1	100.00
		dma_csr_aliasing	6.000s	278.722us	1	1	100.00
		dma_same_csr_outstanding	6.000s	250.030us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	22.000s	196.514us	1	1	100.00
		dma_generic_stress	5.100m	27.747ms	1	1	100.00
		dma_handshake_stress	2.100m	111.943ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	980.519us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.350m	7.433ms	1	1	100.00
		dma_longer_transfer	29.000s	1.725ms	1	1	100.00
		TOTAL			21	21	100.00