EDN Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.010s	19.279us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.610s	15.089us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.640s	22.444us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.630s	126.203us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.020s	34.284us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.140s	23.385us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.640s	22.444us	1	1	100.00
		edn_csr_aliasing	2.020s	34.284us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.140s	44.448us	1	1	100.00
V2	csrng_commands	edn_genbits	2.140s	44.448us	1	1	100.00
V2	genbits	edn_genbits	2.140s	44.448us	1	1	100.00
V2	interrupts	edn_intr	1.650s	38.166us	1	1	100.00
V2	alerts	edn_alert	2.310s	29.141us	1	1	100.00
V2	errs	edn_err	2.030s	56.658us	1	1	100.00
V2	disable	edn_disable	1.800s	34.161us	1	1	100.00
		edn_disable_auto_req_mode	1.970s	43.701us	1	1	100.00
V2	stress_all	edn_stress_all	3.140s	144.440us	1	1	100.00
V2	intr_test	edn_intr_test	2.060s	20.521us	1	1	100.00
V2	alert_test	edn_alert_test	1.710s	59.567us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.060s	263.139us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.060s	263.139us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.610s	15.089us	1	1	100.00
		edn_csr_rw	1.640s	22.444us	1	1	100.00
		edn_csr_aliasing	2.020s	34.284us	1	1	100.00
		edn_same_csr_outstanding	1.690s	102.916us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.610s	15.089us	1	1	100.00
		edn_csr_rw	1.640s	22.444us	1	1	100.00
		edn_csr_aliasing	2.020s	34.284us	1	1	100.00
		edn_same_csr_outstanding	1.690s	102.916us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.580s	466.256us	1	1	100.00
		edn_tl_intg_err	2.500s	67.594us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	2.010s	51.159us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.310s	29.141us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.580s	466.256us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.580s	466.256us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.580s	466.256us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.580s	466.256us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.310s	29.141us	1	1	100.00
		edn_sec_cm	6.580s	466.256us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.310s	29.141us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.500s	67.594us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.192m	4.193ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00