HMAC Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.020s 226.712us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.920s 38.646us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.520s 13.677us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.520s 110.724us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.760s 105.788us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.750s 101.941us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.520s 13.677us 1 1 100.00
hmac_csr_aliasing 4.760s 105.788us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 25.780s 1.272ms 1 1 100.00
V2 back_pressure hmac_back_pressure 36.640s 889.637us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.057m 25.209ms 1 1 100.00
hmac_test_sha384_vectors 19.910s 946.266us 1 1 100.00
hmac_test_sha512_vectors 19.900s 2.925ms 1 1 100.00
hmac_test_hmac256_vectors 12.240s 536.227us 1 1 100.00
hmac_test_hmac384_vectors 8.270s 249.797us 1 1 100.00
hmac_test_hmac512_vectors 8.140s 693.642us 1 1 100.00
V2 burst_wr hmac_burst_wr 10.470s 1.991ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 5.810m 2.920ms 1 1 100.00
V2 error hmac_error 15.440s 1.158ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.099m 26.091ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.020s 226.712us 1 1 100.00
hmac_long_msg 25.780s 1.272ms 1 1 100.00
hmac_back_pressure 36.640s 889.637us 1 1 100.00
hmac_datapath_stress 5.810m 2.920ms 1 1 100.00
hmac_burst_wr 10.470s 1.991ms 1 1 100.00
hmac_stress_all 12.984m 90.637ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.020s 226.712us 1 1 100.00
hmac_long_msg 25.780s 1.272ms 1 1 100.00
hmac_back_pressure 36.640s 889.637us 1 1 100.00
hmac_datapath_stress 5.810m 2.920ms 1 1 100.00
hmac_wipe_secret 1.099m 26.091ms 1 1 100.00
hmac_test_sha256_vectors 3.057m 25.209ms 1 1 100.00
hmac_test_sha384_vectors 19.910s 946.266us 1 1 100.00
hmac_test_sha512_vectors 19.900s 2.925ms 1 1 100.00
hmac_test_hmac256_vectors 12.240s 536.227us 1 1 100.00
hmac_test_hmac384_vectors 8.270s 249.797us 1 1 100.00
hmac_test_hmac512_vectors 8.140s 693.642us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.020s 226.712us 1 1 100.00
hmac_long_msg 25.780s 1.272ms 1 1 100.00
hmac_back_pressure 36.640s 889.637us 1 1 100.00
hmac_datapath_stress 5.810m 2.920ms 1 1 100.00
hmac_burst_wr 10.470s 1.991ms 1 1 100.00
hmac_error 15.440s 1.158ms 1 1 100.00
hmac_wipe_secret 1.099m 26.091ms 1 1 100.00
hmac_test_sha256_vectors 3.057m 25.209ms 1 1 100.00
hmac_test_sha384_vectors 19.910s 946.266us 1 1 100.00
hmac_test_sha512_vectors 19.900s 2.925ms 1 1 100.00
hmac_test_hmac256_vectors 12.240s 536.227us 1 1 100.00
hmac_test_hmac384_vectors 8.270s 249.797us 1 1 100.00
hmac_test_hmac512_vectors 8.140s 693.642us 1 1 100.00
hmac_stress_all 12.984m 90.637ms 1 1 100.00
V2 stress_all hmac_stress_all 12.984m 90.637ms 1 1 100.00
V2 alert_test hmac_alert_test 1.470s 14.272us 1 1 100.00
V2 intr_test hmac_intr_test 1.520s 24.392us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.080s 51.082us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.080s 51.082us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.920s 38.646us 1 1 100.00
hmac_csr_rw 1.520s 13.677us 1 1 100.00
hmac_csr_aliasing 4.760s 105.788us 1 1 100.00
hmac_same_csr_outstanding 2.230s 664.250us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.920s 38.646us 1 1 100.00
hmac_csr_rw 1.520s 13.677us 1 1 100.00
hmac_csr_aliasing 4.760s 105.788us 1 1 100.00
hmac_same_csr_outstanding 2.230s 664.250us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.670s 79.898us 1 1 100.00
hmac_tl_intg_err 2.870s 375.074us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.870s 375.074us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.020s 226.712us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.980s 65.771us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 29.470s 7.362ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.180s 43.701us 1 1 100.00
TOTAL 28 28 100.00