I2C Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: `2e10a15`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	14.280s	8.675ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	22.460s	4.287ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.550s	76.663us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.710s	255.718us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.940s	2.994ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.200s	141.968us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.910s	43.101us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.710s	255.718us	1	1	100.00
		i2c_csr_aliasing	2.200s	141.968us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.810s	234.402us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	7.083m	69.086ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	46.190s	26.569ms	1	1	100.00
V2	host_override	i2c_host_override	1.680s	18.210us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.657m	21.000ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	27.700s	3.480ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.890s	213.443us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.400s	395.930us	1	1	100.00
		i2c_host_fifo_reset_rx	4.220s	474.111us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.124m	2.176ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	19.980s	2.492ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.800s	204.099us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.280s	5.311ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	13.859m	63.961ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.960s	4.504ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.280s	1.007ms	1	1	100.00
		i2c_target_intr_smoke	6.070s	2.812ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.110s	389.025us	1	1	100.00
		i2c_target_fifo_reset_tx	1.880s	364.424us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	19.310s	21.800ms	1	1	100.00
		i2c_target_stress_rd	11.280s	1.007ms	1	1	100.00
		i2c_target_intr_stress_wr	16.370s	16.699ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.290s	1.496ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	13.210s	2.998ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.820s	800.521us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.820s	268.469us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.480s	345.354us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.850s	109.042us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	46.190s	26.569ms	1	1	100.00
		i2c_host_perf_precise	3.230s	544.153us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	19.980s	2.492ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.050s	396.039us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.340s	1.709ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.910s	2.236ms	1	1	100.00
		i2c_target_nack_txstretch	2.150s	494.447us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.900s	468.145us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.300s	535.525us	1	1	100.00
V2	alert_test	i2c_alert_test	1.540s	25.719us	1	1	100.00
V2	intr_test	i2c_intr_test	1.520s	32.168us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.870s	137.531us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.870s	137.531us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.550s	76.663us	1	1	100.00
		i2c_csr_rw	1.710s	255.718us	1	1	100.00
		i2c_csr_aliasing	2.200s	141.968us	1	1	100.00
		i2c_same_csr_outstanding	1.880s	185.841us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.550s	76.663us	1	1	100.00
		i2c_csr_rw	1.710s	255.718us	1	1	100.00
		i2c_csr_aliasing	2.200s	141.968us	1	1	100.00
		i2c_same_csr_outstanding	1.880s	185.841us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.090s	71.156us	1	1	100.00
		i2c_sec_cm	1.810s	43.212us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.090s	71.156us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	8.640s	825.265us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.570s	29.245us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	3.860s	795.693us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 2 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.24609054702673678551222711002079787860282341025714494296902138337041432217337
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  29244517 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 63 [0x3f])
  UVM_INFO @  29244517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.86673849318311065064464506701305502598595748773475142972211748420484040045828
    Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 795693186 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @ 795693186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.91372049144458924216849064053036126047319101062579100499982637209620686733960
Line 202, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 69085670359 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3870190

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.93451038414753741521657555046168124715612541351601792483411704634636766183384
    Line 94, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 825264849 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 825264849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```