KEYMGR Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.290s	439.001us	1	1	100.00
V1	random	keymgr_random	4.750s	349.963us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.890s	26.360us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.770s	49.467us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	4.560s	340.720us	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	7.040s	452.382us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.310s	71.778us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.770s	49.467us	1	1	100.00
		keymgr_csr_aliasing	7.040s	452.382us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.910s	200.080us	1	1	100.00
V2	sideload	keymgr_sideload	5.240s	212.730us	1	1	100.00
		keymgr_sideload_kmac	2.600s	90.995us	1	1	100.00
		keymgr_sideload_aes	2.800s	35.220us	1	1	100.00
		keymgr_sideload_otbn	2.910s	151.521us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.770s	137.162us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.380s	77.457us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.810s	55.192us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.030s	378.008us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.520s	176.092us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.260s	147.894us	1	1	100.00
V2	stress_all	keymgr_stress_all	1.476m	4.671ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.700s	16.272us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.700s	16.349us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.230s	229.892us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.230s	229.892us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.890s	26.360us	1	1	100.00
		keymgr_csr_rw	1.770s	49.467us	1	1	100.00
		keymgr_csr_aliasing	7.040s	452.382us	1	1	100.00
		keymgr_same_csr_outstanding	2.320s	42.565us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.890s	26.360us	1	1	100.00
		keymgr_csr_rw	1.770s	49.467us	1	1	100.00
		keymgr_csr_aliasing	7.040s	452.382us	1	1	100.00
		keymgr_same_csr_outstanding	2.320s	42.565us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
		keymgr_tl_intg_err	7.080s	2.484ms	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.480s	242.638us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.480s	242.638us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.480s	242.638us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.480s	242.638us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.210s	4.950ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.080s	2.484ms	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.480s	242.638us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.910s	200.080us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.750s	349.963us	1	1	100.00
		keymgr_csr_rw	1.770s	49.467us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.750s	349.963us	1	1	100.00
		keymgr_csr_rw	1.770s	49.467us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.750s	349.963us	1	1	100.00
		keymgr_csr_rw	1.770s	49.467us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.380s	77.457us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.520s	176.092us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.520s	176.092us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.750s	349.963us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.880s	108.566us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	7.180s	677.672us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.380s	77.457us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	7.180s	677.672us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	7.180s	677.672us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	7.180s	677.672us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.450s	501.355us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	7.180s	677.672us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	4.200s	110.019us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.4824938592719253659159607610530175080182147640022363445733167662609974454010
      Line 312, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 110018960 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 110018960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.20307807939981776382314609367206312139067738492819551162334007187004961471017
      Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
        UVM_ERROR @ 340720258 ps: (keymgr_csr_assert_fpv.sv:430) [ASSERT FAILED] sealing_sw_binding_5_rd_A
        UVM_INFO @ 340720258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---