KMAC/MASKED Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	50.960s	4.982ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.900s	59.008us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.850s	50.330us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.670s	581.738us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.110s	761.741us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.650s	64.284us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.850s	50.330us	1	1	100.00
		kmac_csr_aliasing	7.110s	761.741us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.690s	39.301us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.810s	54.294us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	19.410m	50.923ms	1	1	100.00
V2	burst_write	kmac_burst_write	10.496m	36.989ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.095m	63.101ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.359m	87.739ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.351m	46.457ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.510s	674.693us	1	1	100.00
		kmac_test_vectors_shake_128	2.890m	41.348ms	1	1	100.00
		kmac_test_vectors_shake_256	1.613m	4.825ms	1	1	100.00
		kmac_test_vectors_kmac	3.210s	184.917us	1	1	100.00
		kmac_test_vectors_kmac_xof	4.020s	211.119us	1	1	100.00
V2	sideload	kmac_sideload	1.784m	20.217ms	1	1	100.00
V2	app	kmac_app	58.050s	1.479ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.948m	69.518ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.083m	33.162ms	1	1	100.00
V2	error	kmac_error	4.177m	19.263ms	1	1	100.00
V2	key_error	kmac_key_error	9.120s	9.681ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.270s	122.952us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	29.290s	2.696ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.210s	315.751us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	56.450s	47.707ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.810s	56.260us	1	1	100.00
V2	stress_all	kmac_stress_all	3.875m	10.565ms	0	1	0.00
V2	intr_test	kmac_intr_test	1.620s	20.735us	1	1	100.00
V2	alert_test	kmac_alert_test	1.920s	90.434us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.030s	172.435us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.030s	172.435us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.900s	59.008us	1	1	100.00
		kmac_csr_rw	1.850s	50.330us	1	1	100.00
		kmac_csr_aliasing	7.110s	761.741us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	455.429us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.900s	59.008us	1	1	100.00
		kmac_csr_rw	1.850s	50.330us	1	1	100.00
		kmac_csr_aliasing	7.110s	761.741us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	455.429us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.430s	97.363us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.430s	97.363us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.430s	97.363us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.430s	97.363us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.560s	84.292us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	37.990s	10.695ms	1	1	100.00
		kmac_tl_intg_err	2.120s	122.527us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.120s	122.527us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.810s	56.260us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	50.960s	4.982ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.784m	20.217ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.430s	97.363us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	37.990s	10.695ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	37.990s	10.695ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	37.990s	10.695ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	50.960s	4.982ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.810s	56.260us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	37.990s	10.695ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.681m	17.292ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	50.960s	4.982ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.330s	1.734ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_stress_all has 1 failures.

    • 0.kmac_stress_all.45845134666960216320400845320992796429896107589449322444445073547622030822589
      Line 189, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log

        UVM_ERROR @ 10564667266 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 10564667266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.104245962110282706463489963749485790696825963660750775110969927244859958643332
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @ 122527352 ps: (kmac_csr_assert_fpv.sv:506) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @ 122527352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---