KMAC/UNMASKED Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	43.680s	11.212ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.900s	26.950us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.960s	95.930us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.290s	2.598ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.610s	139.601us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.020s	99.765us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.960s	95.930us	1	1	100.00
		kmac_csr_aliasing	6.610s	139.601us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.560s	10.821us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.980s	223.993us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.021m	20.935ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.790m	112.824ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.090s	10.335ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.510s	701.988us	1	1	100.00
		kmac_test_vectors_sha3_384	16.340s	1.633ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.310s	5.537ms	1	1	100.00
		kmac_test_vectors_shake_128	1.624m	2.222ms	1	1	100.00
		kmac_test_vectors_shake_256	24.897m	249.089ms	1	1	100.00
		kmac_test_vectors_kmac	3.660s	1.068ms	1	1	100.00
		kmac_test_vectors_kmac_xof	2.650s	68.089us	1	1	100.00
V2	sideload	kmac_sideload	1.452m	24.940ms	1	1	100.00
V2	app	kmac_app	1.501m	22.163ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.660s	1.184ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.393m	68.538ms	1	1	100.00
V2	error	kmac_error	5.229m	57.721ms	1	1	100.00
V2	key_error	kmac_key_error	11.060s	1.776ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.820s	303.567us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	7.830s	568.435us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	7.990s	2.145ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	6.930s	1.769ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.210s	49.513us	1	1	100.00
V2	stress_all	kmac_stress_all	4.901m	13.397ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.760s	21.972us	1	1	100.00
V2	alert_test	kmac_alert_test	1.660s	22.664us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.370s	89.555us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.370s	89.555us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.900s	26.950us	1	1	100.00
		kmac_csr_rw	1.960s	95.930us	1	1	100.00
		kmac_csr_aliasing	6.610s	139.601us	1	1	100.00
		kmac_same_csr_outstanding	3.360s	108.451us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.900s	26.950us	1	1	100.00
		kmac_csr_rw	1.960s	95.930us	1	1	100.00
		kmac_csr_aliasing	6.610s	139.601us	1	1	100.00
		kmac_same_csr_outstanding	3.360s	108.451us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.340s	91.990us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.340s	91.990us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.340s	91.990us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.340s	91.990us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.000s	366.917us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	26.380s	2.706ms	1	1	100.00
		kmac_tl_intg_err	5.280s	2.993ms	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.280s	2.993ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.210s	49.513us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	43.680s	11.212ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.452m	24.940ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.340s	91.990us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	26.380s	2.706ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	26.380s	2.706ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	26.380s	2.706ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	43.680s	11.212ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.210s	49.513us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	26.380s	2.706ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	48.750s	7.945ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	43.680s	11.212ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	27.590s	2.833ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.60012314952275980429817991815633199653714754409132308561946592702758512227473
      Line 138, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2833172163 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 2833172163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---