2e10a15| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 40.000s | 1.795ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 3.000s | 13.127us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 40.052us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 57.962us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 13.870us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 779.363ns | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 40.052us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 13.870us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 27.000s | 3.623ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 1.150m | 5.980ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 48.000s | 17.701ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 46.163us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 900.361ns | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 900.361ns | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 3.000s | 13.127us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 40.052us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 13.870us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 23.768us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 3.000s | 13.127us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 40.052us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 13.870us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 23.768us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 35.699us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 3.000s | 5.751us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.72517303431361107252515284108411411031944520349123497904064660759775910523043
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 900361 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xbcc13cb8 a_data = 0x36c5c946 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x67 a_opcode = PutFullData a_user = 0x1abba d_data = 0x21056a8b d_size = 0x1 d_param = 0x0 d_source = 0xd1 d_opcode = AccessAckData d_error = 0 d_user = 1010110000110 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 900361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.86018558666006905177773444525651726819305719543828915220157187230874759609583
Line 99, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 5750791 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x394351f8 a_data = 0xeee3d71a a_mask = 0x1 a_size = 0x0 a_param = 0x0 a_source = 0x8c a_opcode = PutPartialData a_user = 0x24156 d_data = 0xfdec49fb d_size = 0x3 d_param = 0x0 d_source = 0x99 d_opcode = AccessAck d_error = 0 d_user = 1101101011001 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 5750791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.25810435615786194741135653380946105632578857538036037192365723940792912828856
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 779363 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xca69a6c0 a_data = 0x71757d87 a_mask = 0x4 a_size = 0x2 a_param = 0x0 a_source = 0xb7 a_opcode = Invalid, value: 6 a_user = 0x27d9b d_data = 0x3e4b4a8b d_size = 0x2 d_param = 0x0 d_source = 0x9f d_opcode = AccessAckData d_error = 0 d_user = 111100110010 d_sink = 0 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 779363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---