OTBN Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	53.108us	1	1	100.00
V1	single_binary	otbn_single	9.000s	17.093us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	53.087us	1	1	100.00
V1	csr_rw	otbn_csr_rw	5.000s	36.960us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	137.000us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	20.182us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	34.384us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	36.960us	1	1	100.00
		otbn_csr_aliasing	7.000s	20.182us	1	1	100.00
V1	mem_walk	otbn_mem_walk	21.000s	366.856us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	13.000s	1.501ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	25.000s	75.570us	1	1	100.00
V2	multi_error	otbn_multi_err	1.217m	355.845us	1	1	100.00
V2	back_to_back	otbn_multi	16.000s	85.209us	1	1	100.00
V2	stress_all	otbn_stress_all	49.000s	388.025us	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	54.337us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	49.752us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	16.000s	290.053us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	23.151us	1	1	100.00
V2	intr_test	otbn_intr_test	7.000s	14.545us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	102.950us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	102.950us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	53.087us	1	1	100.00
		otbn_csr_rw	5.000s	36.960us	1	1	100.00
		otbn_csr_aliasing	7.000s	20.182us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	12.643us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	53.087us	1	1	100.00
		otbn_csr_rw	5.000s	36.960us	1	1	100.00
		otbn_csr_aliasing	7.000s	20.182us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	12.643us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	18.958us	1	1	100.00
		otbn_dmem_err	12.000s	49.431us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	54.954us	1	1	100.00
		otbn_controller_ispr_rdata_err	11.000s	39.365us	1	1	100.00
		otbn_mac_bignum_acc_err	9.000s	93.359us	1	1	100.00
		otbn_urnd_err	7.000s	16.184us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	80.168us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	13.352us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	24.703us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
		otbn_tl_intg_err	17.000s	2.063ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	18.000s	167.746us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	53.108us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	49.431us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	18.958us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	17.000s	2.063ms	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	54.337us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	18.958us	1	1	100.00
		otbn_dmem_err	12.000s	49.431us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	49.752us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	80.168us	1	1	100.00
		otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	17.093us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	18.958us	1	1	100.00
		otbn_dmem_err	12.000s	49.431us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	49.752us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	80.168us	1	1	100.00
		otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	54.337us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	18.958us	1	1	100.00
		otbn_dmem_err	12.000s	49.431us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	49.752us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	80.168us	1	1	100.00
		otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	17.093us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	25.101us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	50.810us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	54.000s	185.585us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	54.000s	185.585us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	23.084us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	9.000s	201.270us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	34.086us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	34.086us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	19.338us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	17.093us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	17.093us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	17.093us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	16.000s	85.209us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	17.093us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	17.093us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	18.452us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	17.093us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	16.283m	9.081ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.250m	426.012us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.92724929041149681219952864905092335215773114671932239607724592006865063172263
      Line 164, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 426011512 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 426011512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.69979713739414193593174521415032675202510345140363711257931088600854448396525
      Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19337562 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  19337562 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  19337562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---