ROM_CTRL/64KB Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.570s 299.711us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.190s 1.499ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.110s 676.722us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.160s 298.882us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.830s 1.067ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.190s 2.366ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.110s 676.722us 1 1 100.00
rom_ctrl_csr_aliasing 6.830s 1.067ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.590s 699.028us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.560s 1.028ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.350s 388.347us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 23.030s 835.187us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 12.300s 1.881ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.710s 210.759us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.610s 1.030ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.610s 1.030ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.190s 1.499ms 1 1 100.00
rom_ctrl_csr_rw 6.110s 676.722us 1 1 100.00
rom_ctrl_csr_aliasing 6.830s 1.067ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.510s 796.743us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.190s 1.499ms 1 1 100.00
rom_ctrl_csr_rw 6.110s 676.722us 1 1 100.00
rom_ctrl_csr_aliasing 6.830s 1.067ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.510s 796.743us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 38.050s 1.570ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.174m 725.743us 1 1 100.00
rom_ctrl_tl_intg_err 1.185m 526.522us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.174m 725.743us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.174m 725.743us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.174m 725.743us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.174m 725.743us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.570s 299.711us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.570s 299.711us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.570s 299.711us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.185m 526.522us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
rom_ctrl_kmac_err_chk 12.300s 1.881ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.197m 7.793ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 38.050s 1.570ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.174m 725.743us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.716m 7.783ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00