RV_TIMER Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.460s	12.565us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.430s	53.037us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.580s	14.525us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.330s	153.754us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.640s	38.803us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.900s	43.033us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.580s	14.525us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	38.803us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.540s	388.738us	1	1	100.00
V2	disabled	rv_timer_disabled	2.630s	2.622ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.730s	532.888us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.730s	532.888us	1	1	100.00
V2	stress	rv_timer_stress_all	3.870s	3.076ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.360s	61.581us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.570s	14.805us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.110s	75.454us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.110s	75.454us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.430s	53.037us	1	1	100.00
		rv_timer_csr_rw	1.580s	14.525us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	38.803us	1	1	100.00
		rv_timer_same_csr_outstanding	1.730s	58.064us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.430s	53.037us	1	1	100.00
		rv_timer_csr_rw	1.580s	14.525us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	38.803us	1	1	100.00
		rv_timer_same_csr_outstanding	1.730s	58.064us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.030s	337.614us	1	1	100.00
		rv_timer_tl_intg_err	1.980s	332.643us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.980s	332.643us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	4.040s	530.572us	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.480s	12.979us	1	1	100.00
		rv_timer_max	1.460s	12.872us	1	1	100.00
		TOTAL			19	19	100.00