SPI_DEVICE/1R1W Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.623m	47.410ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.080s	61.955us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.620s	96.175us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.160s	11.291ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.220s	217.401us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.330s	47.955us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.620s	96.175us	1	1	100.00
		spi_device_csr_aliasing	10.220s	217.401us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.530s	31.546us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.640s	29.262us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.850s	18.724us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.940s	8.105us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.980s	6.439us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.080s	48.252us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.080s	48.252us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	17.300s	114.784ms	1	1	100.00
		spi_device_tpm_sts_read	1.740s	110.272us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	6.750s	5.386ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	14.420s	15.061ms	1	1	100.00
		spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	11.290s	29.569ms	1	1	100.00
		spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	11.290s	29.569ms	1	1	100.00
		spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	20.780s	3.062ms	1	1	100.00
		spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	20.780s	3.062ms	1	1	100.00
		spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	20.780s	3.062ms	1	1	100.00
		spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	20.780s	3.062ms	1	1	100.00
		spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	20.780s	3.062ms	1	1	100.00
		spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	15.730s	63.384ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	17.770s	3.449ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	17.770s	3.449ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	17.770s	3.449ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	5.080s	194.447us	1	1	100.00
		spi_device_read_buffer_direct	6.680s	1.478ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	17.770s	3.449ms	1	1	100.00
		spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	38.110s	19.066ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.280s	751.520us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.280s	751.520us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.623m	47.410ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.085m	6.328ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.719m	106.020ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.640s	21.276us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.550s	19.373us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.910s	302.154us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.910s	302.154us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.080s	61.955us	1	1	100.00
		spi_device_csr_rw	2.620s	96.175us	1	1	100.00
		spi_device_csr_aliasing	10.220s	217.401us	1	1	100.00
		spi_device_same_csr_outstanding	3.110s	42.038us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.080s	61.955us	1	1	100.00
		spi_device_csr_rw	2.620s	96.175us	1	1	100.00
		spi_device_csr_aliasing	10.220s	217.401us	1	1	100.00
		spi_device_same_csr_outstanding	3.110s	42.038us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.000s	153.438us	1	1	100.00
		spi_device_tl_intg_err	7.260s	6.786ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	7.260s	6.786ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.810m	93.278ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.61232793537052401239575265125309771957548579761035634243461009009576777308091
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4985290 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[43])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4985290 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4985290 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[939])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.12346368041561214062185892844222553284194926769429812989103519607033711325485
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4034049 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6c1add [11011000001101011011101] vs 0x0 [0])
        UVM_ERROR @   4064049 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcd0363 [110011010000001101100011] vs 0x0 [0])
        UVM_ERROR @   4068049 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc9d7bf [110010011101011110111111] vs 0x0 [0])
        UVM_ERROR @   4142049 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5bf5bd [10110111111010110111101] vs 0x0 [0])
        UVM_ERROR @   4147049 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x67b90d [11001111011100100001101] vs 0x0 [0])