SPI_HOST Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	19.000s	190.151us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	37.803us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	23.730us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	35.722us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	103.209us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	33.403us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	23.730us	1	1	100.00
		spi_host_csr_aliasing	4.000s	103.209us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	3.000s	15.336us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	75.079us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	8.000s	95.503us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	9.000s	1.723ms	1	1	100.00
		spi_host_error_cmd	4.000s	17.246us	1	1	100.00
		spi_host_event	8.000s	6.529ms	1	1	100.00
V2	clock_rate	spi_host_speed	14.000s	276.852us	1	1	100.00
V2	speed	spi_host_speed	14.000s	276.852us	1	1	100.00
V2	chip_select_timing	spi_host_speed	14.000s	276.852us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	14.000s	554.800us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	27.308us	1	1	100.00
V2	cpol_cpha	spi_host_speed	14.000s	276.852us	1	1	100.00
V2	full_cycle	spi_host_speed	14.000s	276.852us	1	1	100.00
V2	duplex	spi_host_smoke	19.000s	190.151us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	19.000s	190.151us	1	1	100.00
V2	stress_all	spi_host_stress_all	8.000s	1.351ms	1	1	100.00
V2	spien	spi_host_spien	7.000s	1.520ms	1	1	100.00
V2	stall	spi_host_status_stall	47.000s	6.252ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	1.215ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	9.000s	1.723ms	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	32.526us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	20.336us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	68.608us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	68.608us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	37.803us	1	1	100.00
		spi_host_csr_rw	3.000s	23.730us	1	1	100.00
		spi_host_csr_aliasing	4.000s	103.209us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	88.773us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	37.803us	1	1	100.00
		spi_host_csr_rw	3.000s	23.730us	1	1	100.00
		spi_host_csr_aliasing	4.000s	103.209us	1	1	100.00
		spi_host_same_csr_outstanding	3.000s	88.773us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	350.036us	1	1	100.00
		spi_host_sec_cm	4.000s	343.694us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	350.036us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.317m	5.638ms	1	1	100.00
		TOTAL			26	26	100.00