SRAM_CTRL/MAIN Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.660s	848.539us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.650s	74.633us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.520s	15.276us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.150s	44.042us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.600s	17.966us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.880s	368.072us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.520s	15.276us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	17.966us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.752m	14.719ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.065m	24.547ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.820s	3.908ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.457m	45.353ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	6.658m	61.595ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	43.450s	1.786ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	41.270s	34.447ms	1	1	100.00
V2	executable	sram_ctrl_executable	14.217m	23.651ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.280s	4.384ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.226m	76.804ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	21.320s	747.585us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	6.220s	2.331ms	1	1	100.00
		sram_ctrl_throughput_w_readback	13.240s	2.914ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	19.410s	1.871ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.070s	375.850us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	36.924m	218.023ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.610s	16.830us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.970s	1.255ms	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.970s	1.255ms	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.650s	74.633us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	15.276us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	17.966us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.840s	113.131us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.650s	74.633us	1	1	100.00
		sram_ctrl_csr_rw	1.520s	15.276us	1	1	100.00
		sram_ctrl_csr_aliasing	1.600s	17.966us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.840s	113.131us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.710s	14.823ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.420s	1.161us	0	1	0.00
		sram_ctrl_tl_intg_err	2.970s	384.550us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.420s	1.161us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.970s	384.550us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.410s	1.871ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.410s	1.871ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.520s	15.276us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	14.217m	23.651ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	14.217m	23.651ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	14.217m	23.651ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	41.270s	34.447ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.270s	2.799ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.710s	14.823ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.450s	2.665ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.660s	848.539us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.660s	848.539us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	14.217m	23.651ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.420s	1.161us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	41.270s	34.447ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.420s	1.161us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.420s	1.161us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.660s	848.539us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.420s	1.161us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	50.730s	14.872ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.55735700713279701540814243485074626703997202861731572743587489859881031151778
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1161233 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1161233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---