UART Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: 2e10a15

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	9.860s	5.809ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.630s	41.146us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.510s	23.929us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.980s	37.254us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.510s	28.644us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.600s	120.771us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.510s	23.929us	1	1	100.00
		uart_csr_aliasing	1.510s	28.644us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	14.000s	29.109ms	1	1	100.00
V2	parity	uart_smoke	9.860s	5.809ms	1	1	100.00
		uart_tx_rx	14.000s	29.109ms	1	1	100.00
V2	parity_error	uart_intr	9.130s	14.526ms	1	1	100.00
		uart_rx_parity_err	28.270s	48.864ms	1	1	100.00
V2	watermark	uart_tx_rx	14.000s	29.109ms	1	1	100.00
		uart_intr	9.130s	14.526ms	1	1	100.00
V2	fifo_full	uart_fifo_full	22.680s	20.502ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	29.930s	173.262ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	51.830s	44.981ms	1	1	100.00
V2	rx_frame_err	uart_intr	9.130s	14.526ms	1	1	100.00
V2	rx_break_err	uart_intr	9.130s	14.526ms	1	1	100.00
V2	rx_timeout	uart_intr	9.130s	14.526ms	1	1	100.00
V2	perf	uart_perf	5.475m	10.400ms	1	1	100.00
V2	sys_loopback	uart_loopback	7.040s	7.883ms	1	1	100.00
V2	line_loopback	uart_loopback	7.040s	7.883ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	51.940s	144.440ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.078m	51.505ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.030s	1.691ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	47.740s	7.259ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.744m	123.532ms	1	1	100.00
V2	stress_all	uart_stress_all	57.360s	165.639ms	1	1	100.00
V2	alert_test	uart_alert_test	1.760s	58.366us	1	1	100.00
V2	intr_test	uart_intr_test	1.370s	13.604us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.170s	110.271us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.170s	110.271us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.630s	41.146us	1	1	100.00
		uart_csr_rw	1.510s	23.929us	1	1	100.00
		uart_csr_aliasing	1.510s	28.644us	1	1	100.00
		uart_same_csr_outstanding	1.360s	37.230us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.630s	41.146us	1	1	100.00
		uart_csr_rw	1.510s	23.929us	1	1	100.00
		uart_csr_aliasing	1.510s	28.644us	1	1	100.00
		uart_same_csr_outstanding	1.360s	37.230us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.740s	243.923us	1	1	100.00
		uart_tl_intg_err	1.720s	166.651us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.720s	166.651us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	24.390s	3.157ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00