CHIP Simulation Results

Wednesday June 04 2025 17:09:38 UTC

GitHub Revision: `2e10a15`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.019m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.019m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.092m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.263m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.349m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.655m	6.134ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.655m	6.134ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.655m	6.134ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	38.640s	10.240us	0	1	0.00
		chip_sw_example_manufacturer	26.637s		0	1	0.00
		chip_sw_example_concurrency	4.570m	5.661ms	1	1	100.00
		chip_sw_uart_smoketest_signed	15.483s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	13.390s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	13.980s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	13.980s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.310s	11.682us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.743m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.271m	6.660ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.519m	5.459ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	32.533s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	10.795s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.219m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.102m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.490s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.490s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.806m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.438m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.197m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.197m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.979m	4.296ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.462m	3.072ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.926m	14.541ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.183s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.555s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	16.690m	19.308ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.151m	4.401ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.701m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.701m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.552s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.633m	5.611ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.633m	5.611ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.451m	18.016ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.641m	4.434ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.263m	4.573ms	1	1	100.00
		chip_sw_aes_idle	3.575m	5.464ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.260m	4.548ms	1	1	100.00
		chip_sw_kmac_idle	3.675m	4.669ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.377m	12.021ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.513m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.630m	12.017ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.222m	12.015ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.602s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.746s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.497s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.839s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.347s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.764s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.088s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.602s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.746s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.497s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.839s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.347s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.764s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.088s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.632s		0	1	0.00
		chip_sw_aes_enc_jitter_en	50.760s	10.380us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	49.280s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.940s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.195m	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.899s		0	1	0.00
		chip_sw_clkmgr_jitter	4.821m	5.996ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.049m	3.469ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.183s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	47.230s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	46.780s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	48.160s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	51.880s	10.100us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	56.580s	10.120us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.728s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.429s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.188s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.154s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.747m	14.419ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.783m	12.674ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.633m	5.611ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.750s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.783m	12.674ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	41.151s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.481s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.959s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.974s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	12.385s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.747m	14.419ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.926m	14.541ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.808m	20.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.205m	8.248ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.209m	10.413ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.620m	5.448ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.747m	14.419ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.557s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.012s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.747m	14.419ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.644s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.209m	10.413ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.955s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.598s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.661s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.518s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.518s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.573s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.012s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.374s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	26.259s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.374s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.374s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.374s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.637m	5.402ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.845s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.791s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	24.414s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.742s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.374s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.009m	8.467ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.425m	13.761ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	10.947s		0	1	0.00
		chip_prim_tl_access	10.808m	22.280ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.602s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.746s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.497s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.839s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.347s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.764s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.088s		0	1	0.00
		chip_rv_dm_lc_disabled	16.690m	19.308ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.506m	4.824ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	50.760s	10.380us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.964m	4.507ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.575m	5.464ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.468m	3.855ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	49.280s	10.320us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.260m	4.548ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.918m	3.736ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.662m	6.136ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.195m	10.360us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.009m	8.467ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.374s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	43.900s	10.180us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.728m	5.903ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.675m	4.669ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.913s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.913s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	15.504s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.166m	4.425ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.283s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.009m	8.467ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.940s	10.320us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.143s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.632s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.263m	4.573ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.263m	4.573ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.263m	4.573ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.148m	4.816ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.425m	13.761ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.425m	13.761ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.384m	9.762ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.899s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.947s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.747m	14.419ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.197m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.374s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	6.148m	4.816ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.009m	8.467ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.384m	9.762ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.818m	3.401ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	6.148m	4.816ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.009m	8.467ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.384m	9.762ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.818m	3.401ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.374s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.579s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	26.259s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.845s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.791s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	24.414s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.742s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.374s		0	1	0.00
		chip_prim_tl_access	10.808m	22.280ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	10.808m	22.280ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	20.353s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	16.267s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.429s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.632s		0	1	0.00
		chip_sw_aes_enc_jitter_en	50.760s	10.380us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	49.280s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.940s	10.320us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.195m	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.899s		0	1	0.00
		chip_sw_clkmgr_jitter	4.821m	5.996ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.475m	9.363ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.475m	9.363ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.610m	4.615ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.359m	4.826ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.551m	4.746ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.476m	6.768ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.602m	4.751ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.194m	6.238ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.818m	3.401ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.808m	20.016ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.808m	20.016ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.283m	4.677ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.229m	4.238ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.187m	4.316ms	1	1	100.00
		chip_sw_csrng_smoketest	3.758m	3.110ms	1	1	100.00
		chip_sw_gpio_smoketest	4.460m	4.388ms	1	1	100.00
		chip_sw_hmac_smoketest	4.719m	4.797ms	1	1	100.00
		chip_sw_kmac_smoketest	4.245m	4.332ms	1	1	100.00
		chip_sw_otbn_smoketest	4.502m	5.438ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.538m	5.440ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.352m	4.524ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.143m	6.256ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.383m	4.784ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.322m	4.401ms	1	1	100.00
		chip_sw_uart_smoketest	4.290m	5.497ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	13.535s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	15.483s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.743m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.219s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.424m	4.290ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.320m	4.801ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.952m	4.954ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.596m	4.199ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	44.119s		0	1	0.00
		chip_rv_dm_lc_disabled	16.690m	19.308ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	30.963s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.225s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	21.713s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.687s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	44.119s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.206s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.324s		0	1	0.00
		rom_volatile_raw_unlock	11.178s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	16.489s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.564m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.645m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.169m	3.011ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.169m	3.011ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	13.980s		0	1	0.00
		chip_same_csr_outstanding	15.760s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	13.980s		0	1	0.00
		chip_same_csr_outstanding	15.760s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	8.910s	9.517us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	11.370s	13.336us	1	1	100.00
		xbar_smoke_large_delays	4.180m	2.212ms	1	1	100.00
		xbar_smoke_slow_rsp	5.358m	2.044ms	1	1	100.00
		xbar_random_zero_delays	31.320s	25.083us	1	1	100.00
		xbar_random_large_delays	13.381m	6.639ms	1	1	100.00
		xbar_random_slow_rsp	30.608m	11.814ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.615m	193.438us	1	1	100.00
		xbar_error_and_unmapped_addr	45.480s	113.398us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	24.830s	28.934us	1	1	100.00
		xbar_error_and_unmapped_addr	45.480s	113.398us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.819m	98.633us	1	1	100.00
		xbar_access_same_device_slow_rsp	48.946m	19.733ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.407m	248.146us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	8.422m	1.317ms	1	1	100.00
		xbar_stress_all_with_error	2.612m	172.083us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	22.947m	2.619ms	1	1	100.00
		xbar_stress_all_with_reset_error	30.828m	3.632ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.397s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.366s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.517s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.851s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.203s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.080s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.027s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.500s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.973s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.757s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.267s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.371s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.099s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.617s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.029s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.399s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.204s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.463s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.808s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.075s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.323s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	14.398s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.273s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.755s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.675s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.225s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.527s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.119s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.648s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.405s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.890s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.559s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.529s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.655s		0	1	0.00
		rom_e2e_asm_init_dev	11.268s		0	1	0.00
		rom_e2e_asm_init_prod	11.252s		0	1	0.00
		rom_e2e_asm_init_prod_end	10.895s		0	1	0.00
		rom_e2e_asm_init_rma	11.222s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.156s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.878s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.933s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.334s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.026m	3.463ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.281m	5.566ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.452s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.019s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.629s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.875s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.747m	14.419ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	24.887s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.889m	12.954ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	9.865s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.881s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.452s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.019s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.629s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.717s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.721s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.925s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.160m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	18.517m	14.793ms	1	1	100.00
		chip_plic_all_irqs_0	9.527m	5.787ms	1	1	100.00
		chip_plic_all_irqs_10	9.584m	6.540ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.250m	4.713ms	1	1	100.00
		chip_sw_dma_abort	4.229m	3.229ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.520s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.761s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.347s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.941s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.559s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.950s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.815s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.924s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.026s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.153s		0	1	0.00
		chip_sw_mbx_smoketest	4.069m	5.176ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.15261511742188220527372227551823971200137559309263561633674533379292474878137
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (ffa364)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 16.378s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.42179931337436050225565056873115297791184901921165163991608659169754306589786
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (9b60d9)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 121.498s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.77021909026851395196542935415735052076109711626138945095661459243911796395310
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (4be993)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 158.260s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.39426447413720269412857579516379096186250776683687598188522934702833871166898
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (49a269)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 135.274s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.68444982776601977075742170006801768898981241522993231303778442396446893682095
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (64a864)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 110.205s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.72304740219914154187237246395737944176245393972376052613376876726719157961781
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.62849154080796328695350454449735467157562609337898218322930567506632265438429
    Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.22102903348403859423373893693568947525306946731017536532437044507886811712159
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.76678200471417794584422389327054910677820767259304929672806064726295034543834
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.15149415428244787977769828529397228651114709675660101377245388774769144242030
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.720814560040326035853539685354313289033976694197782084153772516561548220490
Line 438, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12020.760713 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12020.760713 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.115681457563468069210016743139710734423949711753929572197452934565207615071242
Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12015.047340 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.047340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.6653501162177361151209812461572213297753175060307204174226521639667690923011
Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12017.216497 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.216497 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.76017703870141741367593367459557254699050741064094531505850080631001615776886
Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12015.330661 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.330661 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.24522845772760939821516963563211368204076314076282858559009937093133870597165
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.66711495953060247763152683363982299564460870511253822678723094238092024254970
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.8692486658427367381563994504703152145590904569478778644925462865058187587761
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.3786274843084258291243506844411436297456575550969759844125032496844624074617
Line 490, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20015.868647 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20015.868647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.38916373570432797115554272112570665211953889079138976557833676572581681667247
Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.045554 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.045554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.87440249874612679766272999314533933172729864109197345401919150909170710568159
Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18015.735717 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.735717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.71541609856595795010777433420979098144903234320532687345675848683458848528147
Line 479, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8467.161640 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (71222883768224130018954311521802418951577794183614099538066959651768407886765 [0x9d76b9416d8c5465fcbf7157c3da58975d179d988ef40e0ef9354c5b630f0bad] vs 92483165132594389335417712007334741509614073839764004353841380839885848731298 [0xcc779dd172d72c9e49f36e710e426549def47e3d16b763a88a6fa0d146745ea2])
  UVM_INFO @ 8467.161640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.34102411022558484483659117849188072425968233757972512061157156652378551511884
Line 487, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5402.250398 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (108995155647318249136127380924571352228269588066922037920681905428777394044297 [0xf0f9126938be80493486b20ed38fef36cd11cf4907444157237ab68db300fd89] vs 59654815621673311267373318254777460863050323124122272305411026863463613143850 [0x83e36dda3868abcef255feff0b424865698febc38aee05b6500bba9020451b2a])
  UVM_INFO @ 5402.250398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.110012293369155468725082797844052666663867491474411358086394149999814568865355
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4296.392905 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h10df2054  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h24  a_opcode: 'h0  a_user: 'h26910  d_param: 'h0  d_source: 'h24  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4296.392905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.102936159509816788403848730156075102018762248058259763475203840525015447135570
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3072.112812 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'hac392225  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h1  a_user: 'h24886  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3072.112812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.66066776205488228786617862444843986447983082017626497099818724515310567877479
    Line 627, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.45761330962611173297397304440579257498359096380465541470491090023630989065645
    Line 479, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5459.369704 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5459.369704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.25381284711293075745511220623915728835451700463225371668003196402510977906372
    Line 686, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10412.711468 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10412.711468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.104766272347686957269526463416203185328064118569319028191351053475790882840251
    Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4615.472960 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4615.472960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.26794482933760990991610520420245652720252948197771150093194099878745808446013
    Line 444, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4826.378834 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4826.378834 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.89816084409347192934662098242784460666658524698344822561132746772505962347847
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5611.088788 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5611.088788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.111430672559271966288219457428615538673641196659896542697807079930823031490713
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6767.534176 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6767.534176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.89092049052437657333221980285114570673615669765816090749358016103748424277058
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.62954617655143128739598349803439702559900597892595727593915664018624969531184
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3011.057556 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3011.057556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.70398005799472508505588310888007700987639579135887986917752415490777206529255
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14540.908340 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14540.908340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.5966163935085754616194569077597739441802990536369591054296657442438069198845
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.99898389409863672281025767318228502040720069119666850044394840551680916836275
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3228.588322 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3228.588322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```