AES/MASKED Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	82.306us	1	1	100.00
V1	smoke	aes_smoke	5.000s	160.696us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	58.325us	1	1	100.00
V1	csr_rw	aes_csr_rw	5.000s	87.836us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	1.429ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	282.284us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	80.326us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	87.836us	1	1	100.00
		aes_csr_aliasing	6.000s	282.284us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	160.696us	1	1	100.00
		aes_config_error	6.000s	452.612us	1	1	100.00
		aes_stress	7.000s	370.323us	1	1	100.00
V2	key_length	aes_smoke	5.000s	160.696us	1	1	100.00
		aes_config_error	6.000s	452.612us	1	1	100.00
		aes_stress	7.000s	370.323us	1	1	100.00
V2	back2back	aes_stress	7.000s	370.323us	1	1	100.00
		aes_b2b	12.000s	627.032us	1	1	100.00
V2	backpressure	aes_stress	7.000s	370.323us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	160.696us	1	1	100.00
		aes_config_error	6.000s	452.612us	1	1	100.00
		aes_stress	7.000s	370.323us	1	1	100.00
		aes_alert_reset	5.000s	154.414us	1	1	100.00
V2	failure_test	aes_man_cfg_err	4.000s	90.248us	1	1	100.00
		aes_config_error	6.000s	452.612us	1	1	100.00
		aes_alert_reset	5.000s	154.414us	1	1	100.00
V2	trigger_clear_test	aes_clear	6.000s	123.458us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	341.794us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	154.414us	1	1	100.00
V2	stress	aes_stress	7.000s	370.323us	1	1	100.00
V2	sideload	aes_stress	7.000s	370.323us	1	1	100.00
		aes_sideload	5.000s	103.976us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	148.194us	1	1	100.00
V2	stress_all	aes_stress_all	42.000s	4.554ms	1	1	100.00
V2	alert_test	aes_alert_test	5.000s	89.083us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	567.389us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	567.389us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	58.325us	1	1	100.00
		aes_csr_rw	5.000s	87.836us	1	1	100.00
		aes_csr_aliasing	6.000s	282.284us	1	1	100.00
		aes_same_csr_outstanding	5.000s	97.617us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	58.325us	1	1	100.00
		aes_csr_rw	5.000s	87.836us	1	1	100.00
		aes_csr_aliasing	6.000s	282.284us	1	1	100.00
		aes_same_csr_outstanding	5.000s	97.617us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	7.000s	139.877us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	434.421us	1	1	100.00
		aes_control_fi	4.000s	49.020us	1	1	100.00
		aes_cipher_fi	4.000s	96.130us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	139.989us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	139.989us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	139.989us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	139.989us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	256.914us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	3.729ms	1	1	100.00
		aes_tl_intg_err	5.000s	291.408us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	291.408us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	154.414us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	139.989us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	160.696us	1	1	100.00
		aes_stress	7.000s	370.323us	1	1	100.00
		aes_alert_reset	5.000s	154.414us	1	1	100.00
		aes_core_fi	5.000s	67.170us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	139.989us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	56.195us	1	1	100.00
		aes_stress	7.000s	370.323us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	370.323us	1	1	100.00
		aes_sideload	5.000s	103.976us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	56.195us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	56.195us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	56.195us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	56.195us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	56.195us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	370.323us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	370.323us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	434.421us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	434.421us	1	1	100.00
		aes_control_fi	4.000s	49.020us	1	1	100.00
		aes_cipher_fi	4.000s	96.130us	1	1	100.00
		aes_ctr_fi	5.000s	77.403us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	434.421us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	434.421us	1	1	100.00
		aes_control_fi	4.000s	49.020us	1	1	100.00
		aes_cipher_fi	4.000s	96.130us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	96.130us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	434.421us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	434.421us	1	1	100.00
		aes_control_fi	4.000s	49.020us	1	1	100.00
		aes_ctr_fi	5.000s	77.403us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	434.421us	1	1	100.00
		aes_control_fi	4.000s	49.020us	1	1	100.00
		aes_cipher_fi	4.000s	96.130us	1	1	100.00
		aes_ctr_fi	5.000s	77.403us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	154.414us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	434.421us	1	1	100.00
		aes_control_fi	4.000s	49.020us	1	1	100.00
		aes_cipher_fi	4.000s	96.130us	1	1	100.00
		aes_ctr_fi	5.000s	77.403us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	434.421us	1	1	100.00
		aes_control_fi	4.000s	49.020us	1	1	100.00
		aes_cipher_fi	4.000s	96.130us	1	1	100.00
		aes_ctr_fi	5.000s	77.403us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	434.421us	1	1	100.00
		aes_control_fi	4.000s	49.020us	1	1	100.00
		aes_ctr_fi	5.000s	77.403us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	434.421us	1	1	100.00
		aes_control_fi	4.000s	49.020us	1	1	100.00
		aes_cipher_fi	4.000s	96.130us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	19.000s	1.921ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.20024882127529890899580138362465947474588848350678652214445423761654479626516
      Line 782, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1920865926 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 1920865926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---