CSRNG Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: `7592556`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	21.703us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	31.169us	1	1	100.00
V1	csr_rw	csrng_csr_rw	4.000s	22.687us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	12.000s	211.393us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	132.799us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	37.577us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	22.687us	1	1	100.00
		csrng_csr_aliasing	9.000s	132.799us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	6.000s	56.271us	0	1	0.00
V2	alerts	csrng_alert	9.000s	310.484us	1	1	100.00
V2	err	csrng_err	5.000s	37.064us	1	1	100.00
V2	cmds	csrng_cmds	53.000s	4.948ms	1	1	100.00
V2	life cycle	csrng_cmds	53.000s	4.948ms	1	1	100.00
V2	stress_all	csrng_stress_all	15.000s	498.164us	1	1	100.00
V2	intr_test	csrng_intr_test	5.000s	38.168us	1	1	100.00
V2	alert_test	csrng_alert_test	5.000s	12.816us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	7.000s	100.841us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	7.000s	100.841us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	31.169us	1	1	100.00
		csrng_csr_rw	4.000s	22.687us	1	1	100.00
		csrng_csr_aliasing	9.000s	132.799us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	96.819us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	31.169us	1	1	100.00
		csrng_csr_rw	4.000s	22.687us	1	1	100.00
		csrng_csr_aliasing	9.000s	132.799us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	96.819us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	7.000s	242.756us	1	1	100.00
		csrng_tl_intg_err	6.000s	67.019us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	19.420us	1	1	100.00
		csrng_csr_rw	4.000s	22.687us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	9.000s	310.484us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	15.000s	498.164us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
		csrng_sec_cm	7.000s	242.756us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
		csrng_sec_cm	7.000s	242.756us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
		csrng_sec_cm	7.000s	242.756us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
		csrng_sec_cm	7.000s	242.756us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
		csrng_sec_cm	7.000s	242.756us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
		csrng_sec_cm	7.000s	242.756us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
		csrng_sec_cm	7.000s	242.756us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	9.000s	310.484us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	15.000s	498.164us	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	9.000s	310.484us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	6.000s	67.019us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
		csrng_sec_cm	7.000s	242.756us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
		csrng_sec_cm	7.000s	242.756us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	56.271us	0	1	0.00
		csrng_err	5.000s	37.064us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	39.000s	1.411ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			17	19	89.47

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_main_sm.sv,35): Assertion u_state_regs_A has failed has 1 failures:

Test csrng_intr has 1 failures.

0.csrng_intr.99912490500150875746577765739837488935510858056952700885683565037020835139500
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 56271174 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @  56271174 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @  56271174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 0.csrng_stress_all_with_rand_reset.84888148193576721519243433058100000660553853280592728503397811513835873571820
    Line 103, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1410675640 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1410675640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```