DMA Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	6.216ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.430ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	342.213us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	19.027us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	24.987us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	7.000s	599.987us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	917.350us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	125.933us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	24.987us	1	1	100.00
		dma_csr_aliasing	6.000s	917.350us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.017m	3.033ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	1.767m	7.801ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	4.783m	54.330ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	5.017m	29.119ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1.767m	7.801ms	1	1	100.00
V2	dma_abort	dma_abort	8.000s	770.060us	1	1	100.00
V2	dma_stress_all	dma_stress_all	45.000s	2.838ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	55.404us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	199.616us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	199.616us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	19.027us	1	1	100.00
		dma_csr_rw	4.000s	24.987us	1	1	100.00
		dma_csr_aliasing	6.000s	917.350us	1	1	100.00
		dma_same_csr_outstanding	5.000s	125.425us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	19.027us	1	1	100.00
		dma_csr_rw	4.000s	24.987us	1	1	100.00
		dma_csr_aliasing	6.000s	917.350us	1	1	100.00
		dma_same_csr_outstanding	5.000s	125.425us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	32.000s	259.481us	1	1	100.00
		dma_generic_stress	5.017m	29.119ms	1	1	100.00
		dma_handshake_stress	1.767m	7.801ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	146.650us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.367m	7.279ms	1	1	100.00
		dma_longer_transfer	6.000s	317.544us	1	1	100.00
		TOTAL			21	21	100.00